[Mlir-commits] [mlir] [mlir][rocdl] Add `readfirstlane` intrinsic (PR #152551)

[Jakub Kuderski]

================
@@ -189,7 +189,21 @@ def ROCDL_BallotOp :
   let assemblyFormat = "$pred attr-dict `:` type($res)";
 }
 
-def ROCDL_ReadlaneOp : ROCDL_IntrOp<"readlane", [], [0], [AllTypesMatch<["res", "src0"]>], 1>,
+def ROCDL_ReadfirstlaneOp : ROCDL_IntrOp<"readfirstlane", [], [0], [AllTypesMatch<["res", "src"]>, Pure], 1>,
----------------
kuhar wrote:

I think you can only hoist it if you can prove the control flow is uniform

https://github.com/llvm/llvm-project/pull/152551