[Mlir-commits] [mlir] [mlir][vector] Add alignment attribute to `maskedload` and `maskedstore` (PR #151690)

Andrzej WarzyƄski llvmlistbot at llvm.org
Mon Aug 4 02:06:54 PDT 2025


================
@@ -1336,6 +1358,28 @@ func.func @maskedload_memref_mismatch(%base: memref<?xf32>, %mask: vector<16xi1>
 
 // -----
 
+//===----------------------------------------------------------------------===//
+// vector.maskedstore
+//===----------------------------------------------------------------------===//
+
+func.func @maskedstore_negative_alignment(%base: memref<?xf32>, %mask: vector<16xi1>, %value: vector<16xf32>) {
+  %c0 = arith.constant 0 : index
+  // expected-error at +1 {{'vector.maskedstore' op attribute 'alignment' failed to satisfy constraint: 64-bit signless integer attribute whose value is positive and whose value is a power of two > 0}}
+  vector.maskedstore %base[%c0], %mask, %value { alignment = -1 } : memref<?xf32>, vector<16xi1>, vector<16xf32> into vector<16xf32>
+  return
+}
+
+// -----
+
+func.func @maskedload_nonpower2_alignment(%base: memref<?xf32>, %mask: vector<16xi1>, %value: vector<16xf32>) {
+  %c0 = arith.constant 0 : index
+  // expected-error at +1 {{'vector.maskedstore' op attribute 'alignment' failed to satisfy constraint: 64-bit signless integer attribute whose value is positive and whose value is a power of two > 0}}
+  vector.maskedstore %base[%c0], %mask, %value { alignment = 3 } : memref<?xf32>, vector<16xi1>, vector<16xf32> into vector<16xf32>
+  return
+}
----------------
banach-space wrote:

I suggest making this test consistent (i.e. identical) with the similar test for `vector.store`: https://github.com/banach-space/llvm-project/blob/34e1224a8bf6d0eb9d3593c95246befba716f590/mlir/test/Dialect/Vector/invalid.mlir#L1935-L1942

Ultimately, this is testing the same logic. Similar comment for `vector.maskedload`. Also, note `@maskedload` in `@maskedload_nonpower2_alignment` ;-)

https://github.com/llvm/llvm-project/pull/151690


More information about the Mlir-commits mailing list