[Mlir-commits] [llvm] [mlir] [AMDGPU][Verifier] Check address space of `alloca` instruction (PR #135820)

[Shilei Tian]

================
@@ -4395,6 +4395,11 @@ void Verifier::visitAllocaInst(AllocaInst &AI) {
     verifySwiftErrorValue(&AI);
   }
 
+  if (TT.isAMDGPU()) {
+    Check(AI.getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS,
+          "alloca on amdgpu must be in addrspace(5)", &AI);
----------------
shiltian wrote:

@nikic I'm thinking about how to update test cases after we extend DL. There are many test cases w/o triple nor data layout, but they have alloca in multiple ASs. After we extend DL, and assert that alloca must be in those ASs, how are we gonna deal with those test  cases? Explicitly add `AX`, `AY`, `AZ`? Also, targets such as NVPTX actually require alloca to be in AS5, but their data layout doesn't have that. They do have a fix-up to convert alloca to AS5. However, if we enforce alloca via DL, it also needs update of the data layout string for NVPTX, which is quite intrusive. I can't speak for NVPTX but it might be quite challenging.

https://github.com/llvm/llvm-project/pull/135820