[Mlir-commits] [mlir] [vector][linearize] Refactor code to push target bit width out of core code (PR #136581)

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git-clang-format --diff HEAD~1 HEAD --extensions cpp,h -- mlir/include/mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp
index 3a80ce815..e24c8ee96 100644
--- a/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp
+++ b/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp
@@ -450,7 +450,7 @@ struct LinearizeVectorBitCast final
 } // namespace
 
 /// If `type` is VectorType with trailing dimension of (bit) size greater than
-/// or equal to `targetBitWidth`, its defining op is considered legal. 
+/// or equal to `targetBitWidth`, its defining op is considered legal.
 static bool legalBecauseOfBitwidth(Type type, unsigned targetBitWidth) {
 
   VectorType vecType = dyn_cast<VectorType>(type);

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https://github.com/llvm/llvm-project/pull/136581