[Mlir-commits] [mlir] [AMDGPU] Implement gpu.subgroup_reduce with DPP intrinsics on AMD GPUs (PR #133204)

[Andrea Faulds]

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@@ -372,6 +500,14 @@ void mlir::populateGpuBreakDownSubgroupReducePatterns(
   patterns.add<ScalarizeSingleElementReduce>(patterns.getContext(), benefit);
 }
 
+void mlir::populateGpuLowerSubgroupReduceToDPPPatterns(
+    RewritePatternSet &patterns, unsigned subgroupSize, amdgpu::Chipset chipset,
+    PatternBenefit benefit) {
+  patterns.add<ScalarSubgroupReduceToDPP>(patterns.getContext(), subgroupSize,
+                                          /*matchClustered=*/true, chipset,
+                                          benefit);
+}
+
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andfau-amd wrote:

I guess for the AMDGPU backend this need for two disjoint sets of patterns doesn't apply, so you could get rid of it in this case maybe? But symmetry with other patterns doesn't hurt and might reduce confusion.

https://github.com/llvm/llvm-project/pull/133204