[Mlir-commits] [mlir] [MLIR][XeGPU] Switch to 1D representation for SIMT code (PR #135116)

[Chao Chen]

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@@ -336,32 +337,30 @@ LogicalResult TensorDescType::verify(
 //        [n_distribution_units, lane_data_size]
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chencha3 wrote:

Updated

https://github.com/llvm/llvm-project/pull/135116