[Mlir-commits] [mlir] [AMDGPU] Implement gpu.subgroup_reduce with DPP intrinsics on AMD GPUs (PR #133204)

[Krzysztof Drewniak]

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@@ -362,6 +365,131 @@ struct VectorSubgroupReduceToShuffles final
   unsigned shuffleBitwidth = 0;
   bool matchClustered = false;
 };
+
+Value createSubgroupDPPReduction(OpBuilder &b, Location loc, Value input,
+                                 gpu::AllReduceOperation mode,
+                                 const ClusterInfo &ci,
+                                 amdgpu::Chipset chipset) {
+  Value dppResult;
+  Value result = input;
+  const int allRows = 0xf;
+  const int allBanks = 0xf;
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krzysz00 wrote:

Nit: these can be constexpr

https://github.com/llvm/llvm-project/pull/133204