[Mlir-commits] [mlir] [AMDGPU] Implement gpu.subgroup_reduce with DPP intrinsics on AMD GPUs (PR #133204)

[Krzysztof Drewniak]

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@@ -70,15 +75,26 @@ struct TestGpuSubgroupReduceLoweringPass
       llvm::cl::desc("Expand subgroup_reduce ops to shuffle ops."),
       llvm::cl::init(false)};
 
+  Option<std::string> target{
+      *this, "target",
+      llvm::cl::desc("Target backend name which will be used to provide "
+                     "compatible lowerings of subgroup reduce."),
+      llvm::cl::init("")};
+
   void runOnOperation() override {
     RewritePatternSet patterns(&getContext());
 
     // Since both pattern sets match on the same ops, set higher benefit to
     // perform fewer failing matches.
     populateGpuBreakDownSubgroupReducePatterns(patterns,
                                                /*maxShuffleBitwidth=*/32,
-                                               PatternBenefit(2));
+                                               PatternBenefit(3));
     if (expandToShuffles) {
+      auto maybeChipset = amdgpu::Chipset::parse(target);
+      if (!failed(maybeChipset)) {
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krzysz00 wrote:

`!failed()` is `succeeded()`

https://github.com/llvm/llvm-project/pull/133204