[Mlir-commits] [mlir] [MLIR][ArmSVE] Add an ArmSVE dialect operation which maps to `svdupq_lane` (PR #135633)

[Andrzej Warzyński]

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@@ -509,6 +524,42 @@ def ScalableMaskedUDivIOp : ScalableMaskedIOp<"masked.divi_unsigned",
 
 def ScalableMaskedDivFOp : ScalableMaskedFOp<"masked.divf", "division">;
 
+def DupQLaneOp : ArmSVE_Op<"dupq_lane", [Pure, AllTypesMatch<["src", "dst"]>]> {
+  let summary = "Broadcast indexed 128-bit segment to vector";
+
+  let description = [{
+    This operation fills each 128-bit segment of a vector with the elements
+    from the indexed 128-bit segment of the source vector. If the VL is
+    128 bits the operation is a NOP. If the index exceeds the number of
+    128-bit segments in a vector the result is an all-zeroes vector.
----------------
banach-space wrote:

> If the index exceeds the number of
    128-bit segments in a vector the result is an all-zeroes vector.
    
Could you mention that this matches the underlying ISA Op semantics? Otherwise it may feel arbitrary. You can also add a link to https://developer.arm.com/documentation/ddi0602/2024-12/SVE-Instructions?lang=en at the top of the file and refer people to that. 

https://github.com/llvm/llvm-project/pull/135633