[Mlir-commits] [mlir] [mlir][gpu] Add address space modifier to Barrier (PR #110527)

Guray Ozen llvmlistbot at llvm.org
Mon Sep 30 11:25:03 PDT 2024


grypp wrote:

I'm not sire I understood the OP semantics. Can we please show how the nvvm lowering will look like? 

Introducing a specific memfence OP would be fine. But we need a RFC if you want to make something complex. 

https://github.com/llvm/llvm-project/pull/110527


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