[Mlir-commits] [mlir] [MLIR][GPU] Lower subgroup query ops in gpu-to-llvm-spv (PR #108839)

[Victor Perez]

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@@ -341,13 +346,21 @@ struct GPUSubgroupOpConversion final : ConvertOpToLLVMPattern<SubgroupOp> {
 
     Operation *moduleOp =
         op->template getParentWithTrait<OpTrait::SymbolTable>();
-    Type resultType = rewriter.getI32Type();
+    Type resultTy = rewriter.getI32Type();
     LLVM::LLVMFuncOp func =
-        lookupOrCreateSPIRVFn(moduleOp, funcName, {}, resultType,
+        lookupOrCreateSPIRVFn(moduleOp, funcName, {}, resultTy,
                               /*isMemNone=*/false, /*isConvergent=*/false);
 
     Location loc = op->getLoc();
     Value result = createSPIRVBuiltinCall(loc, rewriter, func, {}).getResult();
+
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victor-eds wrote:

I mean if we wanna allow other bitwidths (or simply fail instead of asserting). Although OCL-SPV only allows 32 and 64 as of now, it'd be more future-proof.

https://github.com/llvm/llvm-project/pull/108839