[Mlir-commits] [llvm] [mlir] [MLIR][ROCDL] Add dynamically legal ops to LowerGpuOpsToROCDLOpsPass (PR #108302)

[Jakub Kuderski]

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@@ -332,7 +334,13 @@ void mlir::configureGpuToROCDLConversionLegality(ConversionTarget &target) {
   target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::Exp2Op, LLVM::FCeilOp,
                       LLVM::FFloorOp, LLVM::FRemOp, LLVM::LogOp, LLVM::Log10Op,
                       LLVM::Log2Op, LLVM::PowOp, LLVM::SinOp>();
-
+  // These ops are not legal for f64 type but are legal for narrower float
+  // types.
+  target.addDynamicallyLegalOp<LLVM::ExpOp, LLVM::LogOp>([](Operation *op) {
+    return any_of(op->getOperandTypes(), [](Type type) {
+      return isa<FloatType>(type) && type.getIntOrFloatBitWidth() < 64;
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kuhar wrote:

Is this really all small FP types or only f16 and f32? If it's only the two, we can do `llvm::IsaPred<Float16Type, Float32Type>`.

https://github.com/llvm/llvm-project/pull/108302