[Mlir-commits] [mlir] [mlir][LLVMIR] Add more vector predication intrinsic ops (PR #107663)

[Jianjian Guan]

https://github.com/jacquesguan created https://github.com/llvm/llvm-project/pull/107663

This revision adds vector predication smax, smin, umax and umin intrinsic ops.

>From 2cd19e6a9b4c8d5a82fcfd69bdbb25c419aeed28 Mon Sep 17 00:00:00 2001
From: Jianjian GUAN <jacquesguan at me.com>
Date: Fri, 6 Sep 2024 16:15:47 +0800
Subject: [PATCH] [mlir][LLVMIR] Add more vector predication intrinsic ops

This revision adds vector predication smax, smin, umax and umin intrinsic ops.
---
 .../mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td      |  4 ++++
 mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir   | 16 ++++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
index 3822eb3b3f1f6c..5031426033aea1 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
@@ -1156,6 +1156,10 @@ def LLVM_VPShlOp  : LLVM_VPBinaryI<"shl">;
 def LLVM_VPOrOp   : LLVM_VPBinaryI<"or">;
 def LLVM_VPAndOp  : LLVM_VPBinaryI<"and">;
 def LLVM_VPXorOp  : LLVM_VPBinaryI<"xor">;
+def LLVM_VPSMaxOp : LLVM_VPBinaryI<"smax">;
+def LLVM_VPSMinOp : LLVM_VPBinaryI<"smin">;
+def LLVM_VPUMaxOp : LLVM_VPBinaryI<"umax">;
+def LLVM_VPUMinOp : LLVM_VPBinaryI<"umin">;
 
 // Float Binary
 def LLVM_VPFAddOp : LLVM_VPBinaryF<"fadd">;
diff --git a/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
index e2eadf14fc97e9..de0dc8d21584fe 100644
--- a/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
+++ b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
@@ -798,6 +798,18 @@ llvm.func @vector_predication_intrinsics(%A: vector<8xi32>, %B: vector<8xi32>,
   // CHECK: call <8 x i32> @llvm.vp.xor.v8i32
   "llvm.intr.vp.xor" (%A, %B, %mask, %evl) :
          (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
+  // CHECK: call <8 x i32> @llvm.vp.smax.v8i32
+  "llvm.intr.vp.smax" (%A, %B, %mask, %evl) :
+         (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
+  // CHECK: call <8 x i32> @llvm.vp.smin.v8i32
+  "llvm.intr.vp.smin" (%A, %B, %mask, %evl) :
+         (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
+  // CHECK: call <8 x i32> @llvm.vp.umax.v8i32
+  "llvm.intr.vp.umax" (%A, %B, %mask, %evl) :
+         (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
+  // CHECK: call <8 x i32> @llvm.vp.umin.v8i32
+  "llvm.intr.vp.umin" (%A, %B, %mask, %evl) :
+         (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
 
   // CHECK: call <8 x float> @llvm.vp.fadd.v8f32
   "llvm.intr.vp.fadd" (%C, %D, %mask, %evl) :
@@ -1123,6 +1135,10 @@ llvm.func @experimental_constrained_fptrunc(%s: f64, %v: vector<4xf32>) {
 // CHECK-DAG: declare <8 x i32> @llvm.vp.or.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
 // CHECK-DAG: declare <8 x i32> @llvm.vp.and.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
 // CHECK-DAG: declare <8 x i32> @llvm.vp.xor.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
+// CHECK-DAG: declare <8 x i32> @llvm.vp.smax.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
+// CHECK-DAG: declare <8 x i32> @llvm.vp.smin.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
+// CHECK-DAG: declare <8 x i32> @llvm.vp.umax.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
+// CHECK-DAG: declare <8 x i32> @llvm.vp.umin.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
 // CHECK-DAG: declare <8 x float> @llvm.vp.fadd.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)
 // CHECK-DAG: declare <8 x float> @llvm.vp.fsub.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)
 // CHECK-DAG: declare <8 x float> @llvm.vp.fmul.v8f32(<8 x float>, <8 x float>, <8 x i1>, i32)