[Mlir-commits] [mlir] [MLIR][Vector] Update Transfer{Read|Write}DropUnitDimsPattern patterns (PR #112394)

[Han-Chung Wang]

hanhanW wrote:

The error log:

```
zz.mlir:19:7: error: 'vector.mask' op operand #0 must be vector of 1-bit signless integer values, but got 'vector<i1>'
```

https://github.com/llvm/llvm-project/pull/112394