[Mlir-commits] [mlir] [MLIR][ROCDL] Added `SchedGroupBarrier` and `IglpOpt` ops (PR #112237)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Tue Oct 15 10:56:01 PDT 2024
https://github.com/ravil-mobile updated https://github.com/llvm/llvm-project/pull/112237
>From fed2325c003befb1eaac97d3a8f08347e894dce5 Mon Sep 17 00:00:00 2001
From: ravil-mobile <ravil.aviva.com at gmail.com>
Date: Mon, 14 Oct 2024 17:41:54 +0000
Subject: [PATCH] [MLIR][ROCDL] Added `sched.group.barrier` and
`rocdl.iglp.opt`
Currently, the ROCDL dialect contains only `rocdl.sched.barrier` op.
This commit adds missing `sched.group.barrier` and `rocdl.iglp.opt` ops.
The ops are converted to the corresponding intrinsic calls during
the translation from MLIR to LLVM IRs. This intrinsics are hints to
the instruction scheduler of the AMDGPU backend.
---
mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td | 18 ++++++++++++++++++
mlir/test/Dialect/LLVMIR/rocdl.mlir | 12 ++++++++++++
mlir/test/Target/LLVMIR/rocdl.mlir | 16 ++++++++++++++++
3 files changed, 46 insertions(+)
diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
index b80d9ae88910c4..c40ae4b1016b49 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -297,6 +297,24 @@ def ROCDL_SchedBarrier : ROCDL_IntrOp<"sched.barrier", [], [], [], 0>,
"createIntrinsicCall(builder, llvm::Intrinsic::amdgcn_sched_barrier,builder.getInt32(op.getMask()));";
}
+def ROCDL_SchedGroupBarrier : ROCDL_IntrOp<"sched.group.barrier", [], [], [], 0>,
+ Arguments<(ins I32Attr:$mask, I32Attr:$size, I32Attr:$groupId)> {
+ let results = (outs);
+ let assemblyFormat = "$mask `,` $size `,` $groupId attr-dict";
+ string llvmBuilder = [{
+ createIntrinsicCall(builder,
+ llvm::Intrinsic::amdgcn_sched_group_barrier,
+ {builder.getInt32(op.getMask()), builder.getInt32(op.getSize()), builder.getInt32(op.getGroupId())});
+ }];
+}
+
+def ROCDL_IglpOpt : ROCDL_IntrOp<"iglp.opt", [], [], [], 0>,
+ Arguments<(ins I32Attr:$variant)> {
+ let results = (outs);
+ let assemblyFormat = "$variant attr-dict";
+ string llvmBuilder =
+ "createIntrinsicCall(builder, llvm::Intrinsic::amdgcn_iglp_opt,builder.getInt32(op.getVariant()));";
+}
//===---------------------------------------------------------------------===//
// Xdlops intrinsics
diff --git a/mlir/test/Dialect/LLVMIR/rocdl.mlir b/mlir/test/Dialect/LLVMIR/rocdl.mlir
index 397d66d92bc5d5..4afa839aa3ea1b 100644
--- a/mlir/test/Dialect/LLVMIR/rocdl.mlir
+++ b/mlir/test/Dialect/LLVMIR/rocdl.mlir
@@ -41,6 +41,18 @@ func.func @rocdl.sched_barrier() {
llvm.return
}
+func.func @rocdl_sched_group_barrier() {
+ // CHECK: rocdl.sched.group.barrier
+ rocdl.sched.group.barrier 8, 1, 0
+ llvm.return
+}
+
+func.func @rocdl_iglp_opt() {
+ // CHECK: rocdl.iglp.opt
+ rocdl.iglp.opt 0
+ llvm.return
+}
+
func.func @rocdl.setprio() {
// CHECK: rocdl.s.setprio
rocdl.s.setprio 0
diff --git a/mlir/test/Target/LLVMIR/rocdl.mlir b/mlir/test/Target/LLVMIR/rocdl.mlir
index 97276b087b7e93..2f34070147be47 100644
--- a/mlir/test/Target/LLVMIR/rocdl.mlir
+++ b/mlir/test/Target/LLVMIR/rocdl.mlir
@@ -179,6 +179,22 @@ llvm.func @rocdl.schedbarrier() {
llvm.return
}
+llvm.func @rocdl.sched.group.barrier() {
+ // CHECK-LABEL: rocdl.sched.group.barrier
+ // CHECK-NEXT: call void @llvm.amdgcn.sched.group.barrier(i32 8, i32 1, i32 0)
+ rocdl.sched.group.barrier 8, 1, 0
+ llvm.return
+}
+
+llvm.func @rocdl.iglp.opt() {
+ // CHECK-LABEL: rocdl.iglp.opt
+ // CHECK-NEXT: call void @llvm.amdgcn.iglp.opt(i32 0)
+ rocdl.iglp.opt 0
+ // CHECK-NEXT: call void @llvm.amdgcn.iglp.opt(i32 1)
+ rocdl.iglp.opt 1
+ llvm.return
+}
+
llvm.func @rocdl.xdlops(%arg0 : f32, %arg1 : f32,
%arg2 : vector<32 x f32>, %arg3: i32,
%arg4 : vector<16 x f32>, %arg5 : vector<4xf32>,
More information about the Mlir-commits
mailing list