[Mlir-commits] [mlir] [MLIR] Refactor mask compression logic when emulating `vector.maskedload` ops (PR #116520)

[llvmlistbot at llvm.org]

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@@ -605,11 +587,6 @@ struct ConvertVectorMaskedLoad final
   matchAndRewrite(vector::MaskedLoadOp op, OpAdaptor adaptor,
                   ConversionPatternRewriter &rewriter) const override {
 
-    // See #115653
-    if (op.getVectorType().getRank() != 1)
-      return rewriter.notifyMatchFailure(op,
-                                         "only 1-D vectors are supported ATM");
-
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lialan wrote:

I was wrong about this one! I confused the `ConstantMask`'s rank and the extract vector's rank. I reverted it back now.

https://github.com/llvm/llvm-project/pull/116520