[Mlir-commits] [mlir] [mlir] Support ROCDL::ReadlaneOp (PR #116593)
Krzysztof Drewniak
llvmlistbot at llvm.org
Tue Nov 19 11:48:18 PST 2024
================
@@ -197,6 +197,21 @@ def ROCDL_BallotOp :
let assemblyFormat = "$pred attr-dict `:` type($res)";
}
+def ROCDL_ReadlaneOp : ROCDL_IntrOp<"readlane", [], [0], [AllTypesMatch<["res", "src0"]>], 1>,
+ Arguments<(ins LLVM_Type:$src0,
+ I32:$src1)> {
+ let results = (outs LLVM_Type:$res);
+ let summary = "Get the value in the specific lane.";
+
+ let description = [{
+ Get the value in lane `src1` from input `src0`.
+ }];
+
+ let assemblyFormat = [{
+ $src0 `,` $src1 attr-dict `:` `(` type($src0) `,` type($src1) `)` `->` type($res)
----------------
krzysz00 wrote:
You could optionally just use `type($res)` or `type($src0), type($src1)` here, but, ... it's a low-level intrinsic wrapper, it doesn't really matter.
Same for not having the parentheses.
https://github.com/llvm/llvm-project/pull/116593
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