[Mlir-commits] [mlir] [MLIR] extend `getCompressedMaskOp` support in `VectorEmulateNarrowType` (PR #116122)

[Andrzej Warzyński]

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@@ -104,10 +104,14 @@ static FailureOr<Operation *> getCompressedMaskOp(OpBuilder &rewriter,
   if (createMaskOp) {
     OperandRange maskOperands = createMaskOp.getOperands();
     size_t numMaskOperands = maskOperands.size();
+    // The `vector.create_mask` op creates a mask arrangement without any zeros
+    // at the front. Also, because `numFrontPadElems` is strictly smaller than
+    // `numSrcElemsPerDest`, the compressed mask generated by shifting the
+    // original mask by `numFrontPadElems` will not have any zeros at the front
+    // as well.
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banach-space wrote:

It might be just me, but shifting (especially in transformations with low-level Ops like `vector.bitcast`) imply e.g. [arith.shrsi](https://mlir.llvm.org/docs/Dialects/ArithOps/#arithshrsi-arithshrsiop) (or bit shifting in general). Which is not what you meant here, right?

[nit] Removing ambiguity by rephrasing: `shifting` -> `padding`.

https://github.com/llvm/llvm-project/pull/116122