[Mlir-commits] [mlir] [mlir] Support ROCDL::ReadlaneOp (PR #116593)

[Kyle Wang]

================
@@ -197,6 +197,26 @@ def ROCDL_BallotOp :
   let assemblyFormat = "$pred attr-dict `:` type($res)";
 }
 
+def ROCDL_ReadlaneOp : ROCDL_Op<"readlane">,
+  Results<(outs LLVM_Type:$res)>,
+  Arguments<(ins LLVM_Type:$src0,
+                 I32:$src1)> {
+  let summary = "Get the value in the specific lane";
+
+  let description = [{
+    Get the value in lane `src1` from input `src0`.
+  }];
+
+  string llvmBuilder = [{
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knwng wrote:

Just want to double-check, https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/VOP2Instructions.td#L794-L796 shows the output and 1st input have the same type, while https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/IR/IntrinsicsAMDGPU.td#L2161-L2163 doesn't have that constraint. I'm wondering if we should reflect this in rocdl.readlane by adding trait `AllTypesMatch<["res", "src0"]>`.

https://github.com/llvm/llvm-project/pull/116593