[Mlir-commits] [mlir] [mlir][vector] Fix 0-d vector transfer mask inference (PR #116526)

[Andrzej Warzyński]

banach-space wrote:

> I don't really understand why we are forcing a vector<1xi1> mask instead of vector mask. Something seems wrong here.

I’d be cautious about concluding that something is broken - at least not yet! 😊

> I'll take 3 examples:
> ```
> vector.transfer_read %tensor[], permutation_map<() -> (0, 0, 0)> : tensor<f32>, vector<4x4x4xf32>
> vector.transfer_read %tensor[%idx], permutation_map<(d0) -> (0, 0, 0)> : tensor<1xf32>, vector<4x4x4xf32>
> vector.transfer_read %tensor[%idx, %idx2], permutation_map<(d0, d1) -> (0, 0, 0)> : tensor<1x1xf32>, vector<4x4x
> ```

All these examples involve broadcasting. It’s worth referring to this point from the vector.transfer_read [documentation](https://mlir.llvm.org/docs/Dialects/Vector/#vectortransfer_read-vectortransferreadop) (emphasis mine):

> The mask type is an i1 vector with a shape that matches how elements are read from the MemRef/Tensor, **before** any permutation or **broadcasting**. 

This PR strictly follows the documented design, which ensures consistency. Other parts of MLIR should adhere to the same principle as well.

> Based on the definition, the mask dimensionality should always match the dimensionality of the domain.

Which definition? :)

Using `vector<1x1xf32>` instead of `vector<1xf32>` in your 3rd example would be one possibility, but not the only one ;-)

https://github.com/llvm/llvm-project/pull/116526