[Mlir-commits] [mlir] [MLIR] Fix VectorEmulateNarrowType constant op mask bug (PR #116064)

[Han-Chung Wang]

================
@@ -129,6 +132,45 @@ static FailureOr<Operation *> getCompressedMaskOp(OpBuilder &rewriter,
       auto denseAttr = DenseElementsAttr::get(newMaskType, newMaskValues);
       newMask = rewriter.create<arith::ConstantOp>(loc, newMaskType, denseAttr);
     }
+  } else if (constantOp) {
+    assert(shape.size() == 1 && "expected 1-D mask");
----------------
hanhanW wrote:

I don't really know the answer.. My intuition is no in IREE project. My understanding is that all the n-D vector.transfer_read/write ops are unrolled to 1-D vector loads/stores on CPU path before we reach out to the emulation. GPU side, we don't use masking in IREE now.

However, I remember that @dcaballe added some n-D emulation support few months ago, so I'm not sure now.

I'd suggest to move this check before "TypeSwitch" and see what's happening. If it does not break anything, we don't need to make `arith.constant` case special. Otherwise, we leave it to where it is and add a TODO.

What do you think?

https://github.com/llvm/llvm-project/pull/116064