[Mlir-commits] [mlir] [mlir][vector][nfc] Improve comments in `getCompressedMaskOp` (PR #115663)

[llvmlistbot at llvm.org]

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@@ -36,24 +36,33 @@ using namespace mlir;
 #define DBGSNL() (llvm::dbgs() << "\n")
 #define LDBG(X) LLVM_DEBUG(DBGS() << X << "\n")
 
-/// Returns a compressed mask. The mask value is set only if any mask is present
-/// in the scale range. E.g., if `scale` equals to 2, and `intraDataOffset`
-/// equals to 1 (intraDataOffset strictly smaller than scale), the following
-/// mask:
+/// Returns a compressed mask. For example, when emulating `i8` with `i32` and
+/// when the number of source elements spans two `i32` elements, this method
+/// will compress `vector<8xi1>` into `vector<2xi1>`.
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lialan wrote:

@banach-space 

A1: case 1 and case 2 examples are all (what I understand) is correct.
A2: I think it is easier to understand as `8xi8` can bitcast to `2xi32`, which is consistent with the idea.

https://github.com/llvm/llvm-project/pull/115663