[Mlir-commits] [mlir] [mlir][Vector] Remove 0-d corner case condition. (PR #112937)

[Kunwar Grover]

Groverkss wrote:

Nice, the patch is in the right direction. Can you:

- Since the 0-d case is supported now, can you remove the VectorLoadToMemrefLoad/VectorStoreToMemrefStore patterns? This will give you a more accurate view of what needs to be updated.
- Can you check if the test coverage for 0-d transfer_read/transfer_write is enough? If it is enough, please mention it in the PR description and point it out. Otherwise, can you add more tests related to it?

https://github.com/llvm/llvm-project/pull/112937