[Mlir-commits] [mlir] [mlir][Vector] Support 0-d vectors natively in VectorStoreToMemrefStoreLowering. (PR #112937)

[Harrison Hao]

harrisonGPU wrote:

> Thank you for the patch. I think there is a misunderstanding of the issue linked. The issue is about removing this pattern. You can see the comment on VectorLoadToMemrefLoad:
> 
> ```
> /// Replace a 0-d vector.load with a memref.load + vector.broadcast.
> // TODO: we shouldn't cross the vector/scalar domains just for this
> // but atm we lack the infra to avoid it. Possible solutions include:
> // - go directly to LLVM + bitcast
> // - introduce a bitcast op and likely a new pointer dialect
> // - let memref.load/store additionally support the 0-d vector case
> // There are still deeper data layout issues lingering even in this
> // trivial case (for architectures for which this matters).
> ```
> 
> Support non 0-d vectors in this pattern doesn't really get us anything. We want to instead verify if the TransferRead -> vector.load -> LLVM/SPIRV conversions are robust enough to handle 0-d vectorsa and fix them.

Okay, I will consider and verify it. :-)

https://github.com/llvm/llvm-project/pull/112937