[Mlir-commits] [mlir] [MLIR][AMDGPU] Remove support for old llvm.amdgcn.buffer.* intrinsics (PR #93838)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Thu May 30 08:46:07 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mlir-llvm
Author: Jay Foad (jayfoad)
<details>
<summary>Changes</summary>
They have been superseded by llvm.amdgcn.raw.buffer.* and
llvm.amdgcn.struct.buffer.*.
---
Full diff: https://github.com/llvm/llvm-project/pull/93838.diff
4 Files Affected:
- (modified) mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td (-37)
- (modified) mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp (-48)
- (modified) mlir/test/Dialect/LLVMIR/rocdl.mlir (-24)
- (modified) mlir/test/Target/LLVMIR/rocdl.mlir (-25)
``````````diff
diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
index 1dabf5d7979b7..868208ff74a52 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -425,43 +425,6 @@ def ROCDL_RawPtrBufferAtomicUminOp : ROCDL_RawPtrBufferAtomicNoRet<"umin">;
// Note: not supported on all architectures
def ROCDL_RawPtrBufferAtomicFaddOp : ROCDL_RawPtrBufferAtomicNoRet<"fadd">;
-/// LEGACY BUFFER OPERATIONS. DO NOT USE IN NEW CODE. KEPT FOR IR COMPATIBILITY.
-//===---------------------------------------------------------------------===//
-// Vector buffer load/store intrinsics
-
-def ROCDL_MubufLoadOp :
- ROCDL_Op<"buffer.load">,
- Results<(outs LLVM_Type:$res)>,
- Arguments<(ins LLVM_Type:$rsrc,
- LLVM_Type:$vindex,
- LLVM_Type:$offset,
- LLVM_Type:$glc,
- LLVM_Type:$slc)>{
- string llvmBuilder = [{
- $res = createIntrinsicCall(builder,
- llvm::Intrinsic::amdgcn_buffer_load, {$rsrc, $vindex, $offset, $glc,
- $slc}, {$_resultType});
- }];
- let hasCustomAssemblyFormat = 1;
-}
-
-def ROCDL_MubufStoreOp :
- ROCDL_Op<"buffer.store">,
- Arguments<(ins LLVM_Type:$vdata,
- LLVM_Type:$rsrc,
- LLVM_Type:$vindex,
- LLVM_Type:$offset,
- LLVM_Type:$glc,
- LLVM_Type:$slc)>{
- string llvmBuilder = [{
- auto vdataType = moduleTranslation.convertType(op.getVdata().getType());
- createIntrinsicCall(builder,
- llvm::Intrinsic::amdgcn_buffer_store, {$vdata, $rsrc, $vindex,
- $offset, $glc, $slc}, {vdataType});
- }];
- let hasCustomAssemblyFormat = 1;
-}
-
//===---------------------------------------------------------------------===//
// Raw buffer load/store intrinsics
diff --git a/mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
index 65b770ae32610..0c9c61fad1363 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
@@ -39,54 +39,6 @@ using namespace ROCDL;
// Parsing for ROCDL ops
//===----------------------------------------------------------------------===//
-// <operation> ::=
-// `llvm.amdgcn.buffer.load.* %rsrc, %vindex, %offset, %glc, %slc :
-// result_type`
-ParseResult MubufLoadOp::parse(OpAsmParser &parser, OperationState &result) {
- SmallVector<OpAsmParser::UnresolvedOperand, 8> ops;
- Type type;
- if (parser.parseOperandList(ops, 5) || parser.parseColonType(type) ||
- parser.addTypeToList(type, result.types))
- return failure();
-
- MLIRContext *context = parser.getContext();
- auto int32Ty = IntegerType::get(context, 32);
- auto int1Ty = IntegerType::get(context, 1);
- auto i32x4Ty = LLVM::getFixedVectorType(int32Ty, 4);
- return parser.resolveOperands(ops,
- {i32x4Ty, int32Ty, int32Ty, int1Ty, int1Ty},
- parser.getNameLoc(), result.operands);
-}
-
-void MubufLoadOp::print(OpAsmPrinter &p) {
- p << " " << getOperands() << " : " << (*this)->getResultTypes();
-}
-
-// <operation> ::=
-// `llvm.amdgcn.buffer.store.* %vdata, %rsrc, %vindex, %offset, %glc, %slc :
-// result_type`
-ParseResult MubufStoreOp::parse(OpAsmParser &parser, OperationState &result) {
- SmallVector<OpAsmParser::UnresolvedOperand, 8> ops;
- Type type;
- if (parser.parseOperandList(ops, 6) || parser.parseColonType(type))
- return failure();
-
- MLIRContext *context = parser.getContext();
- auto int32Ty = IntegerType::get(context, 32);
- auto int1Ty = IntegerType::get(context, 1);
- auto i32x4Ty = LLVM::getFixedVectorType(int32Ty, 4);
-
- if (parser.resolveOperands(ops,
- {type, i32x4Ty, int32Ty, int32Ty, int1Ty, int1Ty},
- parser.getNameLoc(), result.operands))
- return failure();
- return success();
-}
-
-void MubufStoreOp::print(OpAsmPrinter &p) {
- p << " " << getOperands() << " : " << getVdata().getType();
-}
-
// <operation> ::=
// `llvm.amdgcn.raw.buffer.load.* %rsrc, %offset, %soffset, %aux
// : result_type`
diff --git a/mlir/test/Dialect/LLVMIR/rocdl.mlir b/mlir/test/Dialect/LLVMIR/rocdl.mlir
index 6519186d2cfdc..f5dd5721c45e6 100644
--- a/mlir/test/Dialect/LLVMIR/rocdl.mlir
+++ b/mlir/test/Dialect/LLVMIR/rocdl.mlir
@@ -273,30 +273,6 @@ llvm.func @rocdl.raw.ptr.buffer.i32(%rsrc : !llvm.ptr<8>,
// -----
-// Tests for deprecated buffer ops.
-
-llvm.func @rocdl.mubuf(%rsrc : vector<4xi32>, %vindex : i32,
- %offset : i32, %glc : i1,
- %slc : i1, %vdata1 : vector<1xf32>,
- %vdata2 : vector<2xf32>, %vdata4 : vector<4xf32>) {
- // CHECK-LABEL: rocdl.mubuf
- // CHECK: %{{.*}} = rocdl.buffer.load %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} : vector<1xf32>
- %r1 = rocdl.buffer.load %rsrc, %vindex, %offset, %glc, %slc : vector<1xf32>
- // CHECK: %{{.*}} = rocdl.buffer.load %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} : vector<2xf32>
- %r2 = rocdl.buffer.load %rsrc, %vindex, %offset, %glc, %slc : vector<2xf32>
- // CHECK: %{{.*}} = rocdl.buffer.load %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} : vector<4xf32>
- %r4 = rocdl.buffer.load %rsrc, %vindex, %offset, %glc, %slc : vector<4xf32>
-
- // CHECK: rocdl.buffer.store %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} : vector<1xf32>
- rocdl.buffer.store %vdata1, %rsrc, %vindex, %offset, %glc, %slc : vector<1xf32>
- // CHECK: rocdl.buffer.store %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} : vector<2xf32>
- rocdl.buffer.store %vdata2, %rsrc, %vindex, %offset, %glc, %slc : vector<2xf32>
- // CHECK: rocdl.buffer.store %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} %{{.*}} : vector<4xf32>
- rocdl.buffer.store %vdata4, %rsrc, %vindex, %offset, %glc, %slc : vector<4xf32>
-
- llvm.return
-}
-
llvm.func @rocdl.raw.buffer.f32(%rsrc : vector<4xi32>,
%offset : i32, %soffset : i32,
%aux : i32, %vdata1 : f32,
diff --git a/mlir/test/Target/LLVMIR/rocdl.mlir b/mlir/test/Target/LLVMIR/rocdl.mlir
index ce6b56d48437a..3fd1a5bdbe85e 100644
--- a/mlir/test/Target/LLVMIR/rocdl.mlir
+++ b/mlir/test/Target/LLVMIR/rocdl.mlir
@@ -429,31 +429,6 @@ llvm.func @rocdl.raw.ptr.buffer.atomic.cmpswap(%rsrc : !llvm.ptr<8>,
llvm.return %val : i32
}
-llvm.func @rocdl.mubuf(%rsrc : vector<4xi32>, %vindex : i32,
- %offset : i32, %vdata1 : vector<1xf32>,
- %vdata2 : vector<2xf32>, %vdata4 : vector<4xf32>) {
- %glc = llvm.mlir.constant(false) : i1
- %slc = llvm.mlir.constant(true) : i1
- // CHECK-LABEL: rocdl.mubuf
- // CHECK: call <1 x float> @llvm.amdgcn.buffer.load.v1f32(<4 x i32> %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i1 {{.*}}, i1 {{.*}})
- // CHECK: call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i1 {{.*}}, i1 {{.*}})
- // CHECK: call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i1 {{.*}}, i1 {{.*}})
-
- // CHECK: call void @llvm.amdgcn.buffer.store.v1f32(<1 x float> %{{.*}}, <4 x i32> %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i1 {{.*}}, i1 {{.*}})
- // CHECK: call void @llvm.amdgcn.buffer.store.v2f32(<2 x float> %{{.*}}, <4 x i32> %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i1 {{.*}}, i1 {{.*}})
- // CHECK: call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %{{.*}}, <4 x i32> %{{.*}}, i32 %{{.*}}, i32 %{{.*}}, i1 {{.*}}, i1 {{.*}})
-
- %r1 = rocdl.buffer.load %rsrc, %vindex, %offset, %glc, %slc : vector<1xf32>
- %r2 = rocdl.buffer.load %rsrc, %vindex, %offset, %glc, %slc : vector<2xf32>
- %r4 = rocdl.buffer.load %rsrc, %vindex, %offset, %glc, %slc : vector<4xf32>
-
- rocdl.buffer.store %vdata1, %rsrc, %vindex, %offset, %glc, %slc : vector<1xf32>
- rocdl.buffer.store %vdata2, %rsrc, %vindex, %offset, %glc, %slc : vector<2xf32>
- rocdl.buffer.store %vdata4, %rsrc, %vindex, %offset, %glc, %slc : vector<4xf32>
-
- llvm.return
-}
-
llvm.func @rocdl.raw.buffer(%rsrc : vector<4xi32>,
%offset : i32, %soffset : i32,
%vdata1 : i32,
``````````
</details>
https://github.com/llvm/llvm-project/pull/93838
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