[Mlir-commits] [mlir] [mlir][test] Rename SVE + SME integration tests (nfc) (PR #93521)

Andrzej WarzyƄski llvmlistbot at llvm.org
Wed May 29 11:39:47 PDT 2024


https://github.com/banach-space updated https://github.com/llvm/llvm-project/pull/93521

>From 818bd448d02504a05507c157f5f268feaa9405fe Mon Sep 17 00:00:00 2001
From: Andrzej Warzynski <andrzej.warzynski at arm.com>
Date: Tue, 28 May 2024 10:35:38 +0100
Subject: [PATCH 1/2] [mlir][test] Rename SVE + SME integration tests (nfc)

To keep the test filenames consistent,
  * removes "test-" from  file names (there used to be a mix of
    "test-feature-1.mlir" and "feature-2.mlir"),
  * replaces "_" with "-" (there used to be a mix of "feature-3.mlir"
    and "feature_4.mlir").
---
 .../CPU/ArmSME/{test-load-vertical.mlir => load-vertical.mlir}    | 0
 .../{test-multi-tile-transpose.mlir => multi-tile-transpose.mlir} | 0
 ...st-outerproduct-f16f16f32.mlir => outerproduct-f16f16f32.mlir} | 0
 .../ArmSME/{test-outerproduct-f32.mlir => outerproduct-f32.mlir}  | 0
 .../ArmSME/{test-outerproduct-f64.mlir => outerproduct-f64.mlir}  | 0
 .../{test-outerproduct-i8i8i32.mlir => outerproduct-i8i8i32.mlir} | 0
 .../Dialect/Vector/CPU/ArmSME/{test-ssve.mlir => ssve.mlir}       | 0
 .../Dialect/Vector/CPU/ArmSME/{tile_fill.mlir => tile-fill.mlir}  | 0
 .../ArmSME/{test-transfer-read-2d.mlir => transfer-read-2d.mlir}  | 0
 .../{test-transfer-write-2d.mlir => transfer-write-2d.mlir}       | 0
 .../Vector/CPU/ArmSME/{test-transpose.mlir => transpose.mlir}     | 0
 .../Vector/CPU/ArmSVE/{test-contraction.mlir => contraction.mlir} | 0
 .../{test-scalable-interleave.mlir => scalable-interleave.mlir}   | 0
 .../Dialect/Vector/CPU/ArmSVE/{test-sve.mlir => sve.mlir}         | 0
 14 files changed, 0 insertions(+), 0 deletions(-)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-load-vertical.mlir => load-vertical.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-multi-tile-transpose.mlir => multi-tile-transpose.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-outerproduct-f16f16f32.mlir => outerproduct-f16f16f32.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-outerproduct-f32.mlir => outerproduct-f32.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-outerproduct-f64.mlir => outerproduct-f64.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-outerproduct-i8i8i32.mlir => outerproduct-i8i8i32.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-ssve.mlir => ssve.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{tile_fill.mlir => tile-fill.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-transfer-read-2d.mlir => transfer-read-2d.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-transfer-write-2d.mlir => transfer-write-2d.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-transpose.mlir => transpose.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/{test-contraction.mlir => contraction.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/{test-scalable-interleave.mlir => scalable-interleave.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/{test-sve.mlir => sve.mlir} (100%)

diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-load-vertical.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-load-vertical.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-multi-tile-transpose.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-multi-tile-transpose.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f16f16f32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f16f16f32.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f32.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f64.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f64.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-i8i8i32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-i8i8i32.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-ssve.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-ssve.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile_fill.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile_fill.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-read-2d.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-read-2d.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-write-2d.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-write-2d.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transpose.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transpose.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-contraction.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/contraction.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-contraction.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/contraction.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-scalable-interleave.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/scalable-interleave.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-scalable-interleave.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/scalable-interleave.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-sve.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/sve.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-sve.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/sve.mlir

>From 46a5556e1392f139dfb97680e3d9e34615c0b947 Mon Sep 17 00:00:00 2001
From: Andrzej Warzynski <andrzej.warzynski at arm.com>
Date: Wed, 29 May 2024 19:36:11 +0100
Subject: [PATCH 2/2] fixup! [mlir][test] Rename SVE + SME integration tests
 (nfc)

Rename the remaining Vector (CPU) files
---
 .../Vector/CPU/{test-0-d-vectors.mlir => 0-d-vectors.mlir}        | 0
 .../Vector/CPU/AMX/{test-mulf-full.mlir => mulf-full.mlir}        | 0
 .../Dialect/Vector/CPU/AMX/{test-mulf.mlir => mulf.mlir}          | 0
 .../Dialect/Vector/CPU/AMX/{test-muli-ext.mlir => muli-ext.mlir}  | 0
 .../Vector/CPU/AMX/{test-muli-full.mlir => muli-full.mlir}        | 0
 .../Dialect/Vector/CPU/AMX/{test-muli.mlir => muli.mlir}          | 0
 .../CPU/AMX/{test-tilezero-block.mlir => tilezero-block.mlir}     | 0
 .../Dialect/Vector/CPU/AMX/{test-tilezero.mlir => tilezero.mlir}  | 0
 .../Dialect/Vector/CPU/X86Vector/{test-dot.mlir => dot.mlir}      | 0
 ...nline-asm-vector-avx512.mlir => inline-asm-vector-avx512.mlir} | 0
 .../CPU/X86Vector/{test-mask-compress.mlir => mask-compress.mlir} | 0
 .../Dialect/Vector/CPU/X86Vector/{test-rsqrt.mlir => rsqrt.mlir}  | 0
 .../{test-sparse-dot-product.mlir => sparse-dot-product.mlir}     | 0
 .../{test-vp2intersect-i32.mlir => vp2intersect-i32.mlir}         | 0
 .../Dialect/Vector/CPU/{test-broadcast.mlir => broadcast.mlir}    | 0
 .../Dialect/Vector/CPU/{test-compress.mlir => compress.mlir}      | 0
 .../Vector/CPU/{test-constant-mask.mlir => constant-mask.mlir}    | 0
 .../Vector/CPU/{test-contraction.mlir => contraction.mlir}        | 0
 .../CPU/{test-create-mask-v4i1.mlir => create-mask-v4i1.mlir}     | 0
 .../Vector/CPU/{test-create-mask.mlir => create-mask.mlir}        | 0
 .../Dialect/Vector/CPU/{test-expand.mlir => expand.mlir}          | 0
 ...test-extract-strided-slice.mlir => extract-strided-slice.mlir} | 0
 .../CPU/{test-flat-transpose-col.mlir => flat-transpose-col.mlir} | 0
 .../CPU/{test-flat-transpose-row.mlir => flat-transpose-row.mlir} | 0
 .../Integration/Dialect/Vector/CPU/{test-fma.mlir => fma.mlir}    | 0
 .../Dialect/Vector/CPU/{test-gather.mlir => gather.mlir}          | 0
 .../Vector/CPU/{test-index-vectors.mlir => index-vectors.mlir}    | 0
 .../{test-insert-strided-slice.mlir => insert-strided-slice.mlir} | 0
 .../Dialect/Vector/CPU/{test-interleave.mlir => interleave.mlir}  | 0
 .../Dialect/Vector/CPU/{test-maskedload.mlir => maskedload.mlir}  | 0
 .../Vector/CPU/{test-maskedstore.mlir => maskedstore.mlir}        | 0
 .../{test-matrix-multiply-col.mlir => matrix-multiply-col.mlir}   | 0
 .../{test-matrix-multiply-row.mlir => matrix-multiply-row.mlir}   | 0
 .../CPU/{test-outerproduct-f32.mlir => outerproduct-f32.mlir}     | 0
 .../CPU/{test-outerproduct-i64.mlir => outerproduct-i64.mlir}     | 0
 .../Dialect/Vector/CPU/{test-print-fp.mlir => print-fp.mlir}      | 0
 .../Dialect/Vector/CPU/{test-print-int.mlir => print-int.mlir}    | 0
 .../Dialect/Vector/CPU/{test-print-str.mlir => print-str.mlir}    | 0
 .../Dialect/Vector/CPU/{test-realloc.mlir => realloc.mlir}        | 0
 ...st-reductions-f32-reassoc.mlir => reductions-f32-reassoc.mlir} | 0
 .../Vector/CPU/{test-reductions-f32.mlir => reductions-f32.mlir}  | 0
 ...st-reductions-f64-reassoc.mlir => reductions-f64-reassoc.mlir} | 0
 .../Vector/CPU/{test-reductions-f64.mlir => reductions-f64.mlir}  | 0
 .../Vector/CPU/{test-reductions-i32.mlir => reductions-i32.mlir}  | 0
 .../Vector/CPU/{test-reductions-i4.mlir => reductions-i4.mlir}    | 0
 .../Vector/CPU/{test-reductions-i64.mlir => reductions-i64.mlir}  | 0
 .../Vector/CPU/{test-reductions-si4.mlir => reductions-si4.mlir}  | 0
 .../Vector/CPU/{test-reductions-ui4.mlir => reductions-ui4.mlir}  | 0
 .../{test-rewrite-narrow-types.mlir => rewrite-narrow-types.mlir} | 0
 .../Integration/Dialect/Vector/CPU/{test-scan.mlir => scan.mlir}  | 0
 .../Dialect/Vector/CPU/{test-scatter.mlir => scatter.mlir}        | 0
 .../Dialect/Vector/CPU/{test-shape-cast.mlir => shape-cast.mlir}  | 0
 .../Dialect/Vector/CPU/{test-shuffle.mlir => shuffle.mlir}        | 0
 .../Vector/CPU/{test-shuffle16x16.mlir => shuffle16x16.mlir}      | 0
 .../CPU/{test-sparse-dot-matvec.mlir => sparse-dot-matvec.mlir}   | 0
 ...e-saxpy-jagged-matvec.mlir => sparse-saxpy-jagged-matvec.mlir} | 0
 .../CPU/{test-transfer-read-1d.mlir => transfer-read-1d.mlir}     | 0
 .../CPU/{test-transfer-read-2d.mlir => transfer-read-2d.mlir}     | 0
 .../CPU/{test-transfer-read-3d.mlir => transfer-read-3d.mlir}     | 0
 .../Vector/CPU/{test-transfer-read.mlir => transfer-read.mlir}    | 0
 .../CPU/{test-transfer-to-loops.mlir => transfer-to-loops.mlir}   | 0
 .../Vector/CPU/{test-transfer-write.mlir => transfer-write.mlir}  | 0
 .../Dialect/Vector/CPU/{test-transpose.mlir => transpose.mlir}    | 0
 63 files changed, 0 insertions(+), 0 deletions(-)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-0-d-vectors.mlir => 0-d-vectors.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/AMX/{test-mulf-full.mlir => mulf-full.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/AMX/{test-mulf.mlir => mulf.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/AMX/{test-muli-ext.mlir => muli-ext.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/AMX/{test-muli-full.mlir => muli-full.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/AMX/{test-muli.mlir => muli.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/AMX/{test-tilezero-block.mlir => tilezero-block.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/AMX/{test-tilezero.mlir => tilezero.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/X86Vector/{test-dot.mlir => dot.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/X86Vector/{test-inline-asm-vector-avx512.mlir => inline-asm-vector-avx512.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/X86Vector/{test-mask-compress.mlir => mask-compress.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/X86Vector/{test-rsqrt.mlir => rsqrt.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/X86Vector/{test-sparse-dot-product.mlir => sparse-dot-product.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/X86Vector/{test-vp2intersect-i32.mlir => vp2intersect-i32.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-broadcast.mlir => broadcast.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-compress.mlir => compress.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-constant-mask.mlir => constant-mask.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-contraction.mlir => contraction.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-create-mask-v4i1.mlir => create-mask-v4i1.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-create-mask.mlir => create-mask.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-expand.mlir => expand.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-extract-strided-slice.mlir => extract-strided-slice.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-flat-transpose-col.mlir => flat-transpose-col.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-flat-transpose-row.mlir => flat-transpose-row.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-fma.mlir => fma.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-gather.mlir => gather.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-index-vectors.mlir => index-vectors.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-insert-strided-slice.mlir => insert-strided-slice.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-interleave.mlir => interleave.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-maskedload.mlir => maskedload.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-maskedstore.mlir => maskedstore.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-matrix-multiply-col.mlir => matrix-multiply-col.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-matrix-multiply-row.mlir => matrix-multiply-row.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-outerproduct-f32.mlir => outerproduct-f32.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-outerproduct-i64.mlir => outerproduct-i64.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-print-fp.mlir => print-fp.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-print-int.mlir => print-int.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-print-str.mlir => print-str.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-realloc.mlir => realloc.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-reductions-f32-reassoc.mlir => reductions-f32-reassoc.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-reductions-f32.mlir => reductions-f32.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-reductions-f64-reassoc.mlir => reductions-f64-reassoc.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-reductions-f64.mlir => reductions-f64.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-reductions-i32.mlir => reductions-i32.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-reductions-i4.mlir => reductions-i4.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-reductions-i64.mlir => reductions-i64.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-reductions-si4.mlir => reductions-si4.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-reductions-ui4.mlir => reductions-ui4.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-rewrite-narrow-types.mlir => rewrite-narrow-types.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-scan.mlir => scan.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-scatter.mlir => scatter.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-shape-cast.mlir => shape-cast.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-shuffle.mlir => shuffle.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-shuffle16x16.mlir => shuffle16x16.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-sparse-dot-matvec.mlir => sparse-dot-matvec.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-sparse-saxpy-jagged-matvec.mlir => sparse-saxpy-jagged-matvec.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-transfer-read-1d.mlir => transfer-read-1d.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-transfer-read-2d.mlir => transfer-read-2d.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-transfer-read-3d.mlir => transfer-read-3d.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-transfer-read.mlir => transfer-read.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-transfer-to-loops.mlir => transfer-to-loops.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-transfer-write.mlir => transfer-write.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/{test-transpose.mlir => transpose.mlir} (100%)

diff --git a/mlir/test/Integration/Dialect/Vector/CPU/test-0-d-vectors.mlir b/mlir/test/Integration/Dialect/Vector/CPU/0-d-vectors.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/test-0-d-vectors.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/0-d-vectors.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/AMX/test-mulf-full.mlir b/mlir/test/Integration/Dialect/Vector/CPU/AMX/mulf-full.mlir
similarity index 100%
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