[Mlir-commits] [mlir] [mlir][test] Rename SVE + SME integration tests (nfc) (PR #93521)

[Andrzej Warzyński]

https://github.com/banach-space updated https://github.com/llvm/llvm-project/pull/93521

>From 818bd448d02504a05507c157f5f268feaa9405fe Mon Sep 17 00:00:00 2001
From: Andrzej Warzynski <andrzej.warzynski at arm.com>
Date: Tue, 28 May 2024 10:35:38 +0100
Subject: [PATCH] [mlir][test] Rename SVE + SME integration tests (nfc)

To keep the test filenames consistent,
  * removes "test-" from  file names (there used to be a mix of
    "test-feature-1.mlir" and "feature-2.mlir"),
  * replaces "_" with "-" (there used to be a mix of "feature-3.mlir"
    and "feature_4.mlir").
---
 .../CPU/ArmSME/{test-load-vertical.mlir => load-vertical.mlir}    | 0
 .../{test-multi-tile-transpose.mlir => multi-tile-transpose.mlir} | 0
 ...st-outerproduct-f16f16f32.mlir => outerproduct-f16f16f32.mlir} | 0
 .../ArmSME/{test-outerproduct-f32.mlir => outerproduct-f32.mlir}  | 0
 .../ArmSME/{test-outerproduct-f64.mlir => outerproduct-f64.mlir}  | 0
 .../{test-outerproduct-i8i8i32.mlir => outerproduct-i8i8i32.mlir} | 0
 .../Dialect/Vector/CPU/ArmSME/{test-ssve.mlir => ssve.mlir}       | 0
 .../Dialect/Vector/CPU/ArmSME/{tile_fill.mlir => tile-fill.mlir}  | 0
 .../ArmSME/{test-transfer-read-2d.mlir => transfer-read-2d.mlir}  | 0
 .../{test-transfer-write-2d.mlir => transfer-write-2d.mlir}       | 0
 .../Vector/CPU/ArmSME/{test-transpose.mlir => transpose.mlir}     | 0
 .../Vector/CPU/ArmSVE/{test-contraction.mlir => contraction.mlir} | 0
 .../{test-scalable-interleave.mlir => scalable-interleave.mlir}   | 0
 .../Dialect/Vector/CPU/ArmSVE/{test-sve.mlir => sve.mlir}         | 0
 14 files changed, 0 insertions(+), 0 deletions(-)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-load-vertical.mlir => load-vertical.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-multi-tile-transpose.mlir => multi-tile-transpose.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-outerproduct-f16f16f32.mlir => outerproduct-f16f16f32.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-outerproduct-f32.mlir => outerproduct-f32.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-outerproduct-f64.mlir => outerproduct-f64.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-outerproduct-i8i8i32.mlir => outerproduct-i8i8i32.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-ssve.mlir => ssve.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{tile_fill.mlir => tile-fill.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-transfer-read-2d.mlir => transfer-read-2d.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-transfer-write-2d.mlir => transfer-write-2d.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{test-transpose.mlir => transpose.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/{test-contraction.mlir => contraction.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/{test-scalable-interleave.mlir => scalable-interleave.mlir} (100%)
 rename mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/{test-sve.mlir => sve.mlir} (100%)

diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-load-vertical.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-load-vertical.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-vertical.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-multi-tile-transpose.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-multi-tile-transpose.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/multi-tile-transpose.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f16f16f32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f16f16f32.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f16f16f32.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f32.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f32.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f64.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f64.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-f64.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-i8i8i32.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-i8i8i32.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/outerproduct-i8i8i32.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-ssve.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-ssve.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/ssve.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile_fill.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile_fill.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile-fill.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-read-2d.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-read-2d.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-read-2d.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-write-2d.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-write-2d.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transfer-write-2d.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transpose.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transpose.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-contraction.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/contraction.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-contraction.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/contraction.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-scalable-interleave.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/scalable-interleave.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-scalable-interleave.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/scalable-interleave.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-sve.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/sve.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-sve.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/sve.mlir