[Mlir-commits] [mlir] [mlir][spirv] Add LIT test for vector.interleave to spirv.VectorShuffle (PR #93189)

[Angel Zhang]

https://github.com/angelz913 updated https://github.com/llvm/llvm-project/pull/93189

>From a2178eded56653004e53bab7e0110b7a1ca72a57 Mon Sep 17 00:00:00 2001
From: Angel Zhang <angel.zhang at amd.com>
Date: Thu, 23 May 2024 13:10:37 +0000
Subject: [PATCH 1/3] [MLIR][SPIR-V] Add LIT test for vector.interleave to
 spirv.VectorShuffle

---
 .../Conversion/VectorToSPIRV/vector-to-spirv.mlir    | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir b/mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
index cddc4ee385357..6fb40d2beff1a 100644
--- a/mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
+++ b/mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
@@ -483,6 +483,18 @@ func.func @shuffle(%v0 : vector<1xi32>, %v1: vector<1xi32>) -> vector<2xi32> {
 
 // -----
 
+// CHECK-LABEL: func @interleave
+//  CHECK-SAME: (%[[ARG0:.+]]: vector<2xf32>, %[[ARG1:.+]]: vector<2xf32>)
+//       CHECK: %[[SHUFFLE:.*]] = spirv.VectorShuffle [0 : i32, 2 : i32, 1 : i32, 3 : i32] %[[ARG0]], %[[ARG1]] : vector<2xf32>, vector<2xf32> -> vector<4xf32>
+//       CHECK: return %[[SHUFFLE]]
+func.func @interleave(%a: vector<2xf32>, %b: vector<2xf32>) -> vector<4xf32>
+{
+  %0 = vector.interleave %a, %b : vector<2xf32>
+  return %0 : vector<4xf32>
+}
+
+// -----
+
 // CHECK-LABEL: func @reduction_add
 //  CHECK-SAME: (%[[V:.+]]: vector<4xi32>)
 //       CHECK:   %[[S0:.+]] = spirv.CompositeExtract %[[V]][0 : i32] : vector<4xi32>

>From 6520e545e3a1ac630d43cba84459abb9e5ad6982 Mon Sep 17 00:00:00 2001
From: Angel Zhang <angel.zhang at amd.com>
Date: Thu, 23 May 2024 17:02:22 +0000
Subject: [PATCH 2/3] Rename iaddcarry_extended.mlir to addui_extended.mlir

---
 .../{iaddcarry_extended.mlir => addui_extended.mlir}              | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename mlir/test/mlir-vulkan-runner/{iaddcarry_extended.mlir => addui_extended.mlir} (100%)

diff --git a/mlir/test/mlir-vulkan-runner/iaddcarry_extended.mlir b/mlir/test/mlir-vulkan-runner/addui_extended.mlir
similarity index 100%
rename from mlir/test/mlir-vulkan-runner/iaddcarry_extended.mlir
rename to mlir/test/mlir-vulkan-runner/addui_extended.mlir

>From 9ac1a5608121b8ddd74e3444b514d01c37d4751f Mon Sep 17 00:00:00 2001
From: Angel Zhang <68571948+angelz913 at users.noreply.github.com>
Date: Thu, 23 May 2024 13:11:55 -0400
Subject: [PATCH 3/3] Update
 mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir

Co-authored-by: Jakub Kuderski <kubakuderski at gmail.com>
---
 mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir b/mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
index 6fb40d2beff1a..a7542086aa766 100644
--- a/mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
+++ b/mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir
@@ -487,8 +487,7 @@ func.func @shuffle(%v0 : vector<1xi32>, %v1: vector<1xi32>) -> vector<2xi32> {
 //  CHECK-SAME: (%[[ARG0:.+]]: vector<2xf32>, %[[ARG1:.+]]: vector<2xf32>)
 //       CHECK: %[[SHUFFLE:.*]] = spirv.VectorShuffle [0 : i32, 2 : i32, 1 : i32, 3 : i32] %[[ARG0]], %[[ARG1]] : vector<2xf32>, vector<2xf32> -> vector<4xf32>
 //       CHECK: return %[[SHUFFLE]]
-func.func @interleave(%a: vector<2xf32>, %b: vector<2xf32>) -> vector<4xf32>
-{
+func.func @interleave(%a: vector<2xf32>, %b: vector<2xf32>) -> vector<4xf32> {
   %0 = vector.interleave %a, %b : vector<2xf32>
   return %0 : vector<4xf32>
 }