[Mlir-commits] [mlir] [MLIR][Vector] Implement XferOp To {Load|Store}Lowering as MaskableOpRewritePattern (PR #92892)

[Andrzej Warzyński]

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@@ -392,6 +392,41 @@ func.func @transfer_2D_masked(%mem : memref<?x?xf32>, %mask : vector<2x4xi1>) ->
   return %res : vector<2x4xf32>
 }
 
+// transfer_read/write are lowered to vector.load/store
+// CHECK-LABEL:   func @masked_transfer_to_load(
+//  CHECK-SAME:                                %[[MEM:.*]]: memref<8x8xf32>,
+//  CHECK-SAME:                                %[[IDX:.*]]: index,
+//  CHECK-SAME:                                %[[MASK:.*]]: vector<4xi1>) -> memref<8x8xf32>
+//   CHECK-NOT:      vector.load 
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banach-space wrote:

I don’t quite follow this, the comment above states:
> // transfer_read/write are lowered to vector.load/store

https://github.com/llvm/llvm-project/pull/92892