[Mlir-commits] [mlir] Reimplementing target description concept using DLTI attribute (PR #92138)

[Niranjan Hasabnis]

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@@ -134,6 +136,24 @@ transposePackedMatmul(RewriterBase &rewriter, linalg::LinalgOp linalgOp,
   return packTransposedMatmul;
 }
 
+static SmallVector<int64_t> getDefaultBlockFactors(linalg::LinalgOp linalgOp) {
+  // get L1 cache size first.
+  uint32_t L1_cache_size = 4096; // default value
+  uint32_t cpuID = 0;
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nhasabni wrote:

Yes, will fix the naming issue.

https://github.com/llvm/llvm-project/pull/92138