[Mlir-commits] [mlir] [MLIR][Vector] Implement transferXXPermutationLowering as MaskableOpRewritePattern (PR #91987)

[Hugo Trachino]

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@@ -285,10 +303,14 @@ struct TransferWriteNonPermutationLowering
       newInBoundsValues.push_back(op.isDimInBounds(i));
     }
     ArrayAttr newInBoundsAttr = rewriter.getBoolArrayAttr(newInBoundsValues);
-    rewriter.replaceOpWithNewOp<vector::TransferWriteOp>(
-        op, newVec, op.getSource(), op.getIndices(), AffineMapAttr::get(newMap),
-        newMask, newInBoundsAttr);
-    return success();
+    auto newWrite = rewriter.create<vector::TransferWriteOp>(
+        op.getLoc(), newVec, op.getSource(), op.getIndices(),
+        AffineMapAttr::get(newMap), newMask, newInBoundsAttr);
+    if (newWrite.hasPureTensorSemantics())
+      return newWrite.getResult();
+    // In memref case, MaskableOpRewritePattern cannot replaceOp with result.
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nujaa wrote:

The difference lies in the former `ReplaceOpwithNewOp` from `TransferWritePermutationLowering` and the `replaceOp` from `MaskableOpRewritePattern::MatchAndRewrite`.

https://github.com/llvm/llvm-project/pull/91987