[Mlir-commits] [mlir] [MLIR][Vector] Implement transferXXPermutationLowering as MaskableOpRewritePattern (PR #91987)

[Andrzej Warzyński]

================
@@ -285,10 +303,14 @@ struct TransferWriteNonPermutationLowering
       newInBoundsValues.push_back(op.isDimInBounds(i));
     }
     ArrayAttr newInBoundsAttr = rewriter.getBoolArrayAttr(newInBoundsValues);
-    rewriter.replaceOpWithNewOp<vector::TransferWriteOp>(
-        op, newVec, op.getSource(), op.getIndices(), AffineMapAttr::get(newMap),
-        newMask, newInBoundsAttr);
-    return success();
+    auto newWrite = rewriter.create<vector::TransferWriteOp>(
+        op.getLoc(), newVec, op.getSource(), op.getIndices(),
+        AffineMapAttr::get(newMap), newMask, newInBoundsAttr);
+    if (newWrite.hasPureTensorSemantics())
+      return newWrite.getResult();
+    // In memref case, MaskableOpRewritePattern cannot replaceOp with result.
----------------
banach-space wrote:

I think that this is fine, but how come `permutation_with_mask_xfer_write_fixed_width` works with this change? This doesn't have `PureTensorSemantics`, does it?
```
  vector.transfer_write %vf0, %mem[%base1, %base2], %mask
    {permutation_map = affine_map<(d0, d1) -> (d0)>, in_bounds = [false]}
    : vector<7xf32>, memref<?x?xf32>
```

https://github.com/llvm/llvm-project/pull/91987