[Mlir-commits] [mlir] Reimplementing target description concept using DLTI attribute (PR #92138)

[Adam Siemieniuk]

================
@@ -134,6 +136,24 @@ transposePackedMatmul(RewriterBase &rewriter, linalg::LinalgOp linalgOp,
   return packTransposedMatmul;
 }
 
+static SmallVector<int64_t> getDefaultBlockFactors(linalg::LinalgOp linalgOp) {
+  // get L1 cache size first.
+  uint32_t L1_cache_size = 4096; // default value
+  uint32_t cpuID = 0;
----------------
adam-smnk wrote:

nit: defaulting to device 0 is fine but I wouldn't assume it's a CPU

https://github.com/llvm/llvm-project/pull/92138