[Mlir-commits] [mlir] Reimplementing target description concept using DLTI attribute (PR #92138)

[Renato Golin]

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@@ -134,6 +136,24 @@ transposePackedMatmul(RewriterBase &rewriter, linalg::LinalgOp linalgOp,
   return packTransposedMatmul;
 }
 
+static SmallVector<int64_t> getDefaultBlockFactors(linalg::LinalgOp linalgOp) {
+  // get L1 cache size first.
+  uint32_t L1_cache_size = 4096; // default value
+  uint32_t cpuID = 0;
+  ModuleOp moduleOp = linalgOp->getParentOfType<ModuleOp>();
+  if (std::optional<int64_t> v =
+          DataLayout(moduleOp).getL1CacheSizeInBytes(cpuID)) {
+    L1_cache_size = *v;
+  }
+
+  // block_size = sqrt(L1_cache_size) rounded down to nearest power of 2.
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rengolin wrote:

Naively, we need to keep An, Bn and Cn in cache, so probably this should look into 1/3 of that. Better implementations can stream An/Bn, so can have larger tile sizes, but this is just a default anyway.

https://github.com/llvm/llvm-project/pull/92138