[Mlir-commits] [mlir] [mlir][ArmSME] Verify ops on tile types post LLVM conversion (PR #92076)
Cullen Rhodes
llvmlistbot at llvm.org
Tue May 14 00:31:35 PDT 2024
https://github.com/c-rhodes created https://github.com/llvm/llvm-project/pull/92076
Unsupported ops on tile types can become dead after
`-convert-arm-sme-to-llvm` resulting in incorrect results. Verify such
operations don't exist post-conversion and fail if they do.
Based on discussion from
https://discourse.llvm.org/t/on-improving-arm-sme-lowering-resilience-in-mlir/78543
>From a8a87d4426f1e59ef4932757fd7fa4743d6a1f03 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Tue, 14 May 2024 06:58:02 +0000
Subject: [PATCH 1/2] [mlir][ArmSME] Update ArmSMEToLLVM test to not return
tile types
Use "test.some_use" consistently.
---
.../ArmSMEToLLVM/arm-sme-to-llvm.mlir | 122 ++++++++++--------
1 file changed, 70 insertions(+), 52 deletions(-)
diff --git a/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir b/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir
index f48046a8d7995..81c7844243ead 100644
--- a/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir
+++ b/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir
@@ -630,18 +630,18 @@ func.func @arm_sme_streaming_vl_double_words() -> index {
// CHECK-LABEL: arm_sme_fmopa_2way_f16f16_to_f32
// CHECK: "arm_sme.intr.mopa.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xf16>, vector<[8]xf16>) -> ()
-func.func @arm_sme_fmopa_2way_f16f16_to_f32(%vecA: vector<[8]xf16>, %vecB: vector<[8]xf16>) -> vector<[4]x[4]xf32> {
+func.func @arm_sme_fmopa_2way_f16f16_to_f32(%vecA: vector<[8]xf16>, %vecB: vector<[8]xf16>) {
%result = arm_sme.fmopa_2way %vecA, %vecB : vector<[8]xf16>, vector<[8]xf16> into vector<[4]x[4]xf32>
- return %result : vector<[4]x[4]xf32>
+ "test.some_use"(%result) : (vector<[4]x[4]xf32>) -> ()
}
// -----
// CHECK-LABEL: arm_sme_fmopa_2way_bf16bf16_to_f32
// CHECK: "arm_sme.intr.mopa.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xbf16>, vector<[8]xbf16>) -> ()
-func.func @arm_sme_fmopa_2way_bf16bf16_to_f32(%vecA: vector<[8]xbf16>, %vecB: vector<[8]xbf16>) -> vector<[4]x[4]xf32> {
+func.func @arm_sme_fmopa_2way_bf16bf16_to_f32(%vecA: vector<[8]xbf16>, %vecB: vector<[8]xbf16>) {
%result = arm_sme.fmopa_2way %vecA, %vecB : vector<[8]xbf16>, vector<[8]xbf16> into vector<[4]x[4]xf32>
- return %result : vector<[4]x[4]xf32>
+ "test.some_use"(%result) : (vector<[4]x[4]xf32>) -> ()
}
//===----------------------------------------------------------------------===//
@@ -652,18 +652,18 @@ func.func @arm_sme_fmopa_2way_bf16bf16_to_f32(%vecA: vector<[8]xbf16>, %vecB: ve
// CHECK-LABEL: arm_sme_fmops_2way_f16f16_to_f32
// CHECK: "arm_sme.intr.mops.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xf16>, vector<[8]xf16>) -> ()
-func.func @arm_sme_fmops_2way_f16f16_to_f32(%vecA: vector<[8]xf16>, %vecB: vector<[8]xf16>) -> vector<[4]x[4]xf32> {
+func.func @arm_sme_fmops_2way_f16f16_to_f32(%vecA: vector<[8]xf16>, %vecB: vector<[8]xf16>) {
%result = arm_sme.fmops_2way %vecA, %vecB : vector<[8]xf16>, vector<[8]xf16> into vector<[4]x[4]xf32>
- return %result : vector<[4]x[4]xf32>
+ "test.some_use"(%result) : (vector<[4]x[4]xf32>) -> ()
}
// -----
// CHECK-LABEL: arm_sme_fmops_2way_bf16bf16_to_f32
// CHECK: "arm_sme.intr.mops.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xbf16>, vector<[8]xbf16>) -> ()
-func.func @arm_sme_fmops_2way_bf16bf16_to_f32(%vecA: vector<[8]xbf16>, %vecB: vector<[8]xbf16>) -> vector<[4]x[4]xf32> {
+func.func @arm_sme_fmops_2way_bf16bf16_to_f32(%vecA: vector<[8]xbf16>, %vecB: vector<[8]xbf16>) {
%result = arm_sme.fmops_2way %vecA, %vecB : vector<[8]xbf16>, vector<[8]xbf16> into vector<[4]x[4]xf32>
- return %result : vector<[4]x[4]xf32>
+ "test.some_use"(%result) : (vector<[4]x[4]xf32>) -> ()
}
//===----------------------------------------------------------------------===//
@@ -674,9 +674,9 @@ func.func @arm_sme_fmops_2way_bf16bf16_to_f32(%vecA: vector<[8]xbf16>, %vecB: ve
// CHECK-LABEL: arm_sme_smopa_2way_i16i16_to_i32
// CHECK: "arm_sme.intr.smopa.za32"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xi16>, vector<[8]xi16>) -> ()
-func.func @arm_sme_smopa_2way_i16i16_to_i32(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) -> vector<[4]x[4]xi32> {
+func.func @arm_sme_smopa_2way_i16i16_to_i32(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) {
%result = arm_sme.smopa_2way %vecA, %vecB : vector<[8]xi16>, vector<[8]xi16> into vector<[4]x[4]xi32>
- return %result : vector<[4]x[4]xi32>
+ "test.some_use"(%result) : (vector<[4]x[4]xi32>) -> ()
}
//===----------------------------------------------------------------------===//
@@ -687,9 +687,9 @@ func.func @arm_sme_smopa_2way_i16i16_to_i32(%vecA: vector<[8]xi16>, %vecB: vecto
// CHECK-LABEL: arm_sme_smops_2way_i16i16_to_i32
// CHECK: "arm_sme.intr.smops.za32"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xi16>, vector<[8]xi16>) -> ()
-func.func @arm_sme_smops_2way_i16i16_to_i32(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) -> vector<[4]x[4]xi32> {
+func.func @arm_sme_smops_2way_i16i16_to_i32(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) {
%result = arm_sme.smops_2way %vecA, %vecB : vector<[8]xi16>, vector<[8]xi16> into vector<[4]x[4]xi32>
- return %result : vector<[4]x[4]xi32>
+ "test.some_use"(%result) : (vector<[4]x[4]xi32>) -> ()
}
//===----------------------------------------------------------------------===//
@@ -700,9 +700,10 @@ func.func @arm_sme_smops_2way_i16i16_to_i32(%vecA: vector<[8]xi16>, %vecB: vecto
// CHECK-LABEL: arm_sme_umopa_2way_i16i16_to_i32
// CHECK: "arm_sme.intr.umopa.za32"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xi16>, vector<[8]xi16>) -> ()
-func.func @arm_sme_umopa_2way_i16i16_to_i32(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) -> vector<[4]x[4]xi32> {
+func.func @arm_sme_umopa_2way_i16i16_to_i32(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) {
%result = arm_sme.umopa_2way %vecA, %vecB : vector<[8]xi16>, vector<[8]xi16> into vector<[4]x[4]xi32>
- return %result : vector<[4]x[4]xi32>
+ "test.some_use"(%result) : (vector<[4]x[4]xi32>) -> ()
+ return
}
//===----------------------------------------------------------------------===//
@@ -713,9 +714,10 @@ func.func @arm_sme_umopa_2way_i16i16_to_i32(%vecA: vector<[8]xi16>, %vecB: vecto
// CHECK-LABEL: arm_sme_umops_2way_i16i16_to_i32
// CHECK: "arm_sme.intr.umops.za32"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xi16>, vector<[8]xi16>) -> ()
-func.func @arm_sme_umops_2way_i16i16_to_i32(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) -> vector<[4]x[4]xi32> {
+func.func @arm_sme_umops_2way_i16i16_to_i32(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) {
%result = arm_sme.umops_2way %vecA, %vecB : vector<[8]xi16>, vector<[8]xi16> into vector<[4]x[4]xi32>
- return %result : vector<[4]x[4]xi32>
+ "test.some_use"(%result) : (vector<[4]x[4]xi32>) -> ()
+ return
}
//===----------------------------------------------------------------------===//
@@ -726,18 +728,20 @@ func.func @arm_sme_umops_2way_i16i16_to_i32(%vecA: vector<[8]xi16>, %vecB: vecto
// CHECK-LABEL: arm_sme_smopa_4way_i8i8_to_i32
// CHECK: "arm_sme.intr.smopa.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[16]xi1>, vector<[16]xi1>, vector<[16]xi8>, vector<[16]xi8>) -> ()
-func.func @arm_sme_smopa_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) -> vector<[4]x[4]xi32> {
+func.func @arm_sme_smopa_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) {
%result = arm_sme.smopa_4way %vecA, %vecB : vector<[16]xi8>, vector<[16]xi8> into vector<[4]x[4]xi32>
- return %result : vector<[4]x[4]xi32>
+ "test.some_use"(%result) : (vector<[4]x[4]xi32>) -> ()
+ return
}
// -----
// CHECK-LABEL: arm_sme_smopa_4way_i16i16_to_i64
// CHECK: "arm_sme.intr.smopa.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xi16>, vector<[8]xi16>) -> ()
-func.func @arm_sme_smopa_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) -> vector<[2]x[2]xi64> {
+func.func @arm_sme_smopa_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) {
%result = arm_sme.smopa_4way %vecA, %vecB : vector<[8]xi16>, vector<[8]xi16> into vector<[2]x[2]xi64>
- return %result : vector<[2]x[2]xi64>
+ "test.some_use"(%result) : (vector<[2]x[2]xi64>) -> ()
+ return
}
//===----------------------------------------------------------------------===//
@@ -748,18 +752,20 @@ func.func @arm_sme_smopa_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vecto
// CHECK-LABEL: arm_sme_smops_4way_i8i8_to_i32
// CHECK: "arm_sme.intr.smops.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[16]xi1>, vector<[16]xi1>, vector<[16]xi8>, vector<[16]xi8>) -> ()
-func.func @arm_sme_smops_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) -> vector<[4]x[4]xi32> {
+func.func @arm_sme_smops_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) {
%result = arm_sme.smops_4way %vecA, %vecB : vector<[16]xi8>, vector<[16]xi8> into vector<[4]x[4]xi32>
- return %result : vector<[4]x[4]xi32>
+ "test.some_use"(%result) : (vector<[4]x[4]xi32>) -> ()
+ return
}
// -----
// CHECK-LABEL: arm_sme_smops_4way_i16i16_to_i64
// CHECK: "arm_sme.intr.smops.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xi16>, vector<[8]xi16>) -> ()
-func.func @arm_sme_smops_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) -> vector<[2]x[2]xi64> {
+func.func @arm_sme_smops_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) {
%result = arm_sme.smops_4way %vecA, %vecB : vector<[8]xi16>, vector<[8]xi16> into vector<[2]x[2]xi64>
- return %result : vector<[2]x[2]xi64>
+ "test.some_use"(%result) : (vector<[2]x[2]xi64>) -> ()
+ return
}
//===----------------------------------------------------------------------===//
@@ -770,18 +776,20 @@ func.func @arm_sme_smops_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vecto
// CHECK-LABEL: arm_sme_umopa_4way_i8i8_to_i32
// CHECK: "arm_sme.intr.umopa.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[16]xi1>, vector<[16]xi1>, vector<[16]xi8>, vector<[16]xi8>) -> ()
-func.func @arm_sme_umopa_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) -> vector<[4]x[4]xi32> {
+func.func @arm_sme_umopa_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) {
%result = arm_sme.umopa_4way %vecA, %vecB : vector<[16]xi8>, vector<[16]xi8> into vector<[4]x[4]xi32>
- return %result : vector<[4]x[4]xi32>
+ "test.some_use"(%result) : (vector<[4]x[4]xi32>) -> ()
+ return
}
// -----
// CHECK-LABEL: arm_sme_umopa_4way_i16i16_to_i64
// CHECK: "arm_sme.intr.umopa.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xi16>, vector<[8]xi16>) -> ()
-func.func @arm_sme_umopa_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) -> vector<[2]x[2]xi64> {
+func.func @arm_sme_umopa_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) {
%result = arm_sme.umopa_4way %vecA, %vecB : vector<[8]xi16>, vector<[8]xi16> into vector<[2]x[2]xi64>
- return %result : vector<[2]x[2]xi64>
+ "test.some_use"(%result) : (vector<[2]x[2]xi64>) -> ()
+ return
}
//===----------------------------------------------------------------------===//
@@ -792,18 +800,20 @@ func.func @arm_sme_umopa_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vecto
// CHECK-LABEL: arm_sme_umops_4way_i8i8_to_i32
// CHECK: "arm_sme.intr.umops.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[16]xi1>, vector<[16]xi1>, vector<[16]xi8>, vector<[16]xi8>) -> ()
-func.func @arm_sme_umops_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) -> vector<[4]x[4]xi32> {
+func.func @arm_sme_umops_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) {
%result = arm_sme.umops_4way %vecA, %vecB : vector<[16]xi8>, vector<[16]xi8> into vector<[4]x[4]xi32>
- return %result : vector<[4]x[4]xi32>
+ "test.some_use"(%result) : (vector<[4]x[4]xi32>) -> ()
+ return
}
// -----
// CHECK-LABEL: arm_sme_umops_4way_i16i16_to_i64
// CHECK: "arm_sme.intr.umops.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xi16>, vector<[8]xi16>) -> ()
-func.func @arm_sme_umops_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) -> vector<[2]x[2]xi64> {
+func.func @arm_sme_umops_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) {
%result = arm_sme.umops_4way %vecA, %vecB : vector<[8]xi16>, vector<[8]xi16> into vector<[2]x[2]xi64>
- return %result : vector<[2]x[2]xi64>
+ "test.some_use"(%result) : (vector<[2]x[2]xi64>) -> ()
+ return
}
//===----------------------------------------------------------------------===//
@@ -814,18 +824,20 @@ func.func @arm_sme_umops_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vecto
// CHECK-LABEL: arm_sme_sumopa_4way_i8i8_to_i32
// CHECK: "arm_sme.intr.sumopa.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[16]xi1>, vector<[16]xi1>, vector<[16]xi8>, vector<[16]xi8>) -> ()
-func.func @arm_sme_sumopa_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) -> vector<[4]x[4]xi32> {
+func.func @arm_sme_sumopa_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) {
%result = arm_sme.sumopa_4way %vecA, %vecB : vector<[16]xi8>, vector<[16]xi8> into vector<[4]x[4]xi32>
- return %result : vector<[4]x[4]xi32>
+ "test.some_use"(%result) : (vector<[4]x[4]xi32>) -> ()
+ return
}
// -----
// CHECK-LABEL: arm_sme_sumopa_4way_i16i16_to_i64
// CHECK: "arm_sme.intr.sumopa.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xi16>, vector<[8]xi16>) -> ()
-func.func @arm_sme_sumopa_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) -> vector<[2]x[2]xi64> {
+func.func @arm_sme_sumopa_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) {
%result = arm_sme.sumopa_4way %vecA, %vecB : vector<[8]xi16>, vector<[8]xi16> into vector<[2]x[2]xi64>
- return %result : vector<[2]x[2]xi64>
+ "test.some_use"(%result) : (vector<[2]x[2]xi64>) -> ()
+ return
}
//===----------------------------------------------------------------------===//
@@ -836,18 +848,20 @@ func.func @arm_sme_sumopa_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vect
// CHECK-LABEL: arm_sme_sumops_4way_i8i8_to_i32
// CHECK: "arm_sme.intr.sumops.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[16]xi1>, vector<[16]xi1>, vector<[16]xi8>, vector<[16]xi8>) -> ()
-func.func @arm_sme_sumops_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) -> vector<[4]x[4]xi32> {
+func.func @arm_sme_sumops_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) {
%result = arm_sme.sumops_4way %vecA, %vecB : vector<[16]xi8>, vector<[16]xi8> into vector<[4]x[4]xi32>
- return %result : vector<[4]x[4]xi32>
+ "test.some_use"(%result) : (vector<[4]x[4]xi32>) -> ()
+ return
}
// -----
// CHECK-LABEL: arm_sme_sumops_4way_i16i16_to_i64
// CHECK: "arm_sme.intr.sumops.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xi16>, vector<[8]xi16>) -> ()
-func.func @arm_sme_sumops_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) -> vector<[2]x[2]xi64> {
+func.func @arm_sme_sumops_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) {
%result = arm_sme.sumops_4way %vecA, %vecB : vector<[8]xi16>, vector<[8]xi16> into vector<[2]x[2]xi64>
- return %result : vector<[2]x[2]xi64>
+ "test.some_use"(%result) : (vector<[2]x[2]xi64>) -> ()
+ return
}
//===----------------------------------------------------------------------===//
@@ -858,18 +872,20 @@ func.func @arm_sme_sumops_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vect
// CHECK-LABEL: arm_sme_usmopa_4way_i8i8_to_i32
// CHECK: "arm_sme.intr.usmopa.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[16]xi1>, vector<[16]xi1>, vector<[16]xi8>, vector<[16]xi8>) -> ()
-func.func @arm_sme_usmopa_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) -> vector<[4]x[4]xi32> {
- %reuslt = arm_sme.usmopa_4way %vecA, %vecB : vector<[16]xi8>, vector<[16]xi8> into vector<[4]x[4]xi32>
- return %reuslt : vector<[4]x[4]xi32>
+func.func @arm_sme_usmopa_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) {
+ %result = arm_sme.usmopa_4way %vecA, %vecB : vector<[16]xi8>, vector<[16]xi8> into vector<[4]x[4]xi32>
+ "test.some_use"(%result) : (vector<[4]x[4]xi32>) -> ()
+ return
}
// -----
// CHECK-LABEL: arm_sme_usmopa_4way_i16i16_to_i64
// CHECK: "arm_sme.intr.usmopa.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xi16>, vector<[8]xi16>) -> ()
-func.func @arm_sme_usmopa_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) -> vector<[2]x[2]xi64> {
- %reuslt = arm_sme.usmopa_4way %vecA, %vecB : vector<[8]xi16>, vector<[8]xi16> into vector<[2]x[2]xi64>
- return %reuslt : vector<[2]x[2]xi64>
+func.func @arm_sme_usmopa_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) {
+ %result = arm_sme.usmopa_4way %vecA, %vecB : vector<[8]xi16>, vector<[8]xi16> into vector<[2]x[2]xi64>
+ "test.some_use"(%result) : (vector<[2]x[2]xi64>) -> ()
+ return
}
//===----------------------------------------------------------------------===//
@@ -880,16 +896,18 @@ func.func @arm_sme_usmopa_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vect
// CHECK-LABEL: arm_sme_usmops_4way_i8i8_to_i32
// CHECK: "arm_sme.intr.usmops.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[16]xi1>, vector<[16]xi1>, vector<[16]xi8>, vector<[16]xi8>) -> ()
-func.func @arm_sme_usmops_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) -> vector<[4]x[4]xi32> {
- %reuslt = arm_sme.usmops_4way %vecA, %vecB : vector<[16]xi8>, vector<[16]xi8> into vector<[4]x[4]xi32>
- return %reuslt : vector<[4]x[4]xi32>
+func.func @arm_sme_usmops_4way_i8i8_to_i32(%vecA: vector<[16]xi8>, %vecB: vector<[16]xi8>) {
+ %result = arm_sme.usmops_4way %vecA, %vecB : vector<[16]xi8>, vector<[16]xi8> into vector<[4]x[4]xi32>
+ "test.some_use"(%result) : (vector<[4]x[4]xi32>) -> ()
+ return
}
// -----
// CHECK-LABEL: arm_sme_usmops_4way_i16i16_to_i64
// CHECK: "arm_sme.intr.usmops.wide"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xi16>, vector<[8]xi16>) -> ()
-func.func @arm_sme_usmops_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) -> vector<[2]x[2]xi64> {
- %reuslt = arm_sme.usmops_4way %vecA, %vecB : vector<[8]xi16>, vector<[8]xi16> into vector<[2]x[2]xi64>
- return %reuslt : vector<[2]x[2]xi64>
+func.func @arm_sme_usmops_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vector<[8]xi16>) {
+ %result = arm_sme.usmops_4way %vecA, %vecB : vector<[8]xi16>, vector<[8]xi16> into vector<[2]x[2]xi64>
+ "test.some_use"(%result) : (vector<[2]x[2]xi64>) -> ()
+ return
}
>From ecc60b981af42e8e074e610840745bc58b915bce Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Mon, 13 May 2024 13:51:32 +0000
Subject: [PATCH 2/2] [mlir][ArmSME] Verify ops on tile types post LLVM
conversion
Unsupported ops on tile types can become dead after
`-convert-arm-sme-to-llvm` resulting in incorrect results. Verify such
operations don't exist post-conversion and fail if they do.
Based on discussion from
https://discourse.llvm.org/t/on-improving-arm-sme-lowering-resilience-in-mlir/78543
---
.../Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp | 29 +++++++++++++++++--
.../ArmSMEToLLVM/arm-sme-to-llvm.mlir | 29 +++++++++++++++++++
.../Conversion/ArmSMEToLLVM/unsupported.mlir | 13 +++++++++
3 files changed, 69 insertions(+), 2 deletions(-)
diff --git a/mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp b/mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
index 1ba1b88fc1234..607711abbcda4 100644
--- a/mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
+++ b/mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
@@ -17,6 +17,7 @@
#include "mlir/Dialect/Arith/IR/Arith.h"
#include "mlir/Dialect/ArmSME/IR/ArmSME.h"
#include "mlir/Dialect/ArmSME/Utils/Utils.h"
+#include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h"
#include "mlir/Dialect/Func/IR/FuncOps.h"
#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
#include "mlir/Dialect/MemRef/IR/MemRef.h"
@@ -872,9 +873,33 @@ struct ConvertArmSMEToLLVMPass
configureArmSMEToLLVMConversionLegality(target);
populateArmSMEToLLVMConversionPatterns(converter, patterns);
- if (failed(applyPartialConversion(getOperation(), target,
- std::move(patterns))))
+ Operation *moduleOp = getOperation();
+ if (failed(applyPartialConversion(moduleOp, target, std::move(patterns))))
signalPassFailure();
+
+ // Walk the function(s) and fail if there are unexpected operations on SME
+ // tile types after conversion.
+ moduleOp->walk([&](func::FuncOp funcOp) {
+ funcOp->walk([&](Operation *op) {
+ // These ops are legal post conversion, skip these.
+ // Note: 'test.some_use' is a dummy op we use extensively in the tests
+ // to prevent tile ops being DCE'd.
+ if (isa<arm_sme::MaterializeSSATileOp, cf::BranchOp, scf::ForOp,
+ scf::YieldOp>(op) ||
+ op->getName().getStringRef() == "test.some_use")
+ return;
+ auto isSMETileType = [](Type type) -> bool {
+ auto vecType = dyn_cast<VectorType>(type);
+ return vecType && arm_sme::isValidSMETileVectorType(vecType);
+ };
+ if (llvm::any_of(op->getResultTypes(), isSMETileType) ||
+ llvm::any_of(op->getOperandTypes(), isSMETileType)) {
+ op->emitOpError("unexpected operation with SME tile type after "
+ "conversion to LLVM");
+ signalPassFailure();
+ }
+ });
+ });
}
};
diff --git a/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir b/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir
index 81c7844243ead..d6b7e47b2a765 100644
--- a/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir
+++ b/mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir
@@ -911,3 +911,32 @@ func.func @arm_sme_usmops_4way_i16i16_to_i64(%vecA: vector<[8]xi16>, %vecB: vect
"test.some_use"(%result) : (vector<[2]x[2]xi64>) -> ()
return
}
+
+//===----------------------------------------------------------------------===//
+// Operations on SME tile types allowed after conversion
+//===----------------------------------------------------------------------===//
+
+// -----
+
+// The following operations on SME tile types are permitted after conversion:
+//
+// - arm_sme.materialize_ssa_tile
+// - cf.br
+// - scf.for
+// - scf.yield
+//
+// this test verifies this. Conversion will fail for operations with SME tile
+// types not in this list, this is tested in 'unsupported.mlir'.
+
+func.func @ops_on_tiles_legal_post_conversion(%ub : index) {
+ %c0 = arith.constant 0 : index
+ %c1 = arith.constant 1 : index
+ %tile = arm_sme.materialize_ssa_tile : vector<[4]x[4]xf32>
+ %updated_tile = scf.for %i = %c0 to %ub step %c1 iter_args(%iter_tile = %tile) -> (vector<[4]x[4]xf32>) {
+ scf.yield %iter_tile : vector<[4]x[4]xf32>
+ }
+ cf.br ^bb1(%updated_tile : vector<[4]x[4]xf32>)
+^bb1(%x : vector<[4]x[4]xf32>):
+ "test.some_use"(%x) : (vector<[4]x[4]xf32>) -> ()
+ return
+}
diff --git a/mlir/test/Conversion/ArmSMEToLLVM/unsupported.mlir b/mlir/test/Conversion/ArmSMEToLLVM/unsupported.mlir
index 15767ff1dec3f..53e198cb35b51 100644
--- a/mlir/test/Conversion/ArmSMEToLLVM/unsupported.mlir
+++ b/mlir/test/Conversion/ArmSMEToLLVM/unsupported.mlir
@@ -5,10 +5,23 @@
//===----------------------------------------------------------------------===//
func.func @arm_sme_outerproduct_unsupported_type(%lhs : vector<[16]xi8>, %rhs : vector<[16]xi8>) {
+ // expected-error at below {{unexpected operation with SME tile type after conversion to LLVM}}
%acc = arm_sme.get_tile : vector<[16]x[16]xi8>
+ // expected-error at below {{unexpected operation with SME tile type after conversion to LLVM}}
// expected-error at +2 {{failed to legalize operation 'arm_sme.outerproduct'}}
// expected-error at +1 {{unsupported type}}
%0 = arm_sme.outerproduct %lhs, %rhs acc(%acc) : vector<[16]xi8>, vector<[16]xi8>
"test.some_use"(%0) : (vector<[16]x[16]xi8>) -> ()
}
+//===----------------------------------------------------------------------===//
+// Unsupported operations on SME tile types
+//===----------------------------------------------------------------------===//
+
+// -----
+
+func.func @unsupported_arith_op(%a : vector<[4]x[4]xf32>, %b : vector<[4]x[4]xf32>) {
+ // expected-error at below {{unexpected operation with SME tile type after conversion to LLVM}}
+ %0 = arith.addf %a, %b : vector<[4]x[4]xf32>
+ "test.some_use"(%0) : (vector<[4]x[4]xf32>) -> ()
+}
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