[Mlir-commits] [mlir] [MLIR][Mem2Reg] Improve performance by avoiding recomputations (PR #91444)

[Tobias Gysi]

================
@@ -605,20 +627,24 @@ void MemorySlotPromoter::promoteSlot() {
 
 LogicalResult mlir::tryToPromoteMemorySlots(
     ArrayRef<PromotableAllocationOpInterface> allocators, OpBuilder &builder,
-    const DataLayout &dataLayout, Mem2RegStatistics statistics) {
+    const DataLayout &dataLayout, DominanceInfo &dominance,
+    Mem2RegStatistics statistics) {
   bool promotedAny = false;
 
+  // Cache for block index maps. This is required to avoid expensive
+  // recomputations.
----------------
gysit wrote:

```suggestion
  // A cache that stores deterministic block indices which are used to erase
  // operations in a valid order. The block index maps are computed lazily and cached 
  // to avoid expensive recomputation.
```
nit: I would expand a bit more.

https://github.com/llvm/llvm-project/pull/91444