[Mlir-commits] [llvm] [mlir] Do not trigger UB during AffineExpr parsing. (PR #96896)

[Johannes Reifferscheid]

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@@ -905,10 +921,16 @@ static AffineExpr simplifyCeilDiv(AffineExpr lhs, AffineExpr rhs) {
   if (!rhsConst || rhsConst.getValue() < 1)
     return nullptr;
 
-  if (lhsConst)
+  if (lhsConst) {
+    // divideCeilSigned can only overflow in this case:
+    if (lhsConst.getValue() == std::numeric_limits<int64_t>::min() &&
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jreiffers wrote:

Let's fix that separately? Line 921 seems wrong, it should be checking for == 0.

https://github.com/llvm/llvm-project/pull/96896