[Mlir-commits] [mlir] [MLIR][OpenMP] Lowering support for Order clause in SIMD directive (PR #96866)

[llvmlistbot at llvm.org]

https://github.com/harishch4 created https://github.com/llvm/llvm-project/pull/96866

None

>From 8989703fc4958a79d7492e7a513ce4c55b1c57f6 Mon Sep 17 00:00:00 2001
From: Harish Chambeti <harishcse44 at gmail.com>
Date: Thu, 27 Jun 2024 13:55:36 +0530
Subject: [PATCH] [MLIR][OpenMP] Lowering support for Order clause in SIMD
 directive

---
 .../OpenMP/OpenMPToLLVMIRTranslation.cpp      |  4 +++-
 mlir/test/Target/LLVMIR/openmp-llvm.mlir      | 24 +++++++++++++++++++
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
index eabc4b30f57a9..5b9457f860479 100644
--- a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+++ b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
@@ -1543,7 +1543,9 @@ convertOmpSimd(Operation &opInst, llvm::IRBuilderBase &builder,
       loopInfo, alignedVars,
       simdOp.getIfExpr() ? moduleTranslation.lookupValue(simdOp.getIfExpr())
                          : nullptr,
-      llvm::omp::OrderKind::OMP_ORDER_unknown, simdlen, safelen);
+      simdOp.getOrderVal() ? llvm::omp::OrderKind::OMP_ORDER_concurrent
+                           : llvm::omp::OrderKind::OMP_ORDER_unknown,
+      simdlen, safelen);
 
   builder.restoreIP(afterIP);
   return success();
diff --git a/mlir/test/Target/LLVMIR/openmp-llvm.mlir b/mlir/test/Target/LLVMIR/openmp-llvm.mlir
index a1cc76f9ab770..5b68a25f218c3 100644
--- a/mlir/test/Target/LLVMIR/openmp-llvm.mlir
+++ b/mlir/test/Target/LLVMIR/openmp-llvm.mlir
@@ -826,6 +826,30 @@ llvm.func @simd_if(%arg0: !llvm.ptr {fir.bindc_name = "n"}, %arg1: !llvm.ptr {fi
 
 // -----
 
+// CHECK-LABEL: @simd_order
+llvm.func @simd_order() {
+  %0 = llvm.mlir.constant(1 : i64) : i64
+  %1 = llvm.alloca %0 x i32 {bindc_name = "i", pinned} : (i64) -> !llvm.ptr
+  %2 = llvm.mlir.constant(1 : i64) : i64
+  %3 = llvm.alloca %2 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr
+  %4 = llvm.mlir.constant(1 : i32) : i32
+  %5 = llvm.mlir.constant(10 : i32) : i32
+  %6 = llvm.mlir.constant(1 : i32) : i32
+  omp.simd order(concurrent) safelen(2) {
+    omp.loop_nest (%arg0) : i32 = (%4) to (%5) inclusive step (%6) {
+      llvm.store %arg0, %1 : i32, !llvm.ptr
+      omp.yield
+    }
+  }
+  llvm.return
+}
+// If clause order(concurrent) is specified then the memory instructions
+// are marked parallel even if 'safelen' is finite.
+// CHECK: llvm.loop.parallel_accesses
+// CHECK-NEXT: llvm.loop.vectorize.enable
+// CHECK-NEXT: llvm.loop.vectorize.width{{.*}}i64 2
+// -----
+
 llvm.func @body(i64)
 
 llvm.func @test_omp_wsloop_ordered(%lb : i64, %ub : i64, %step : i64) -> () {