[Mlir-commits] [mlir] [mlir][LLVMIR][OpenMP] fix dominance for reduction init block (PR #96052)

[Kiran Chandramohan]

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@@ -388,8 +388,18 @@ static LogicalResult inlineConvertOmpRegions(
     // be processed multiple times.
     moduleTranslation.forgetMapping(region);
 
-    if (potentialTerminator && potentialTerminator->isTerminator())
-      potentialTerminator->insertAfter(&builder.GetInsertBlock()->back());
+    if (potentialTerminator && potentialTerminator->isTerminator()) {
+      llvm::BasicBlock *block = builder.GetInsertBlock();
+      if (block->empty())
+        // this can happen for really simple reduction init regions e.g.
+        // %0 = llvm.mlir.constant(0 : i32) : i32
+        // omp.yield(%0 : i32)
+        // because the llvm.mlir.constant (MLIR op) isn't converted into any
+        // llvm op
+        potentialTerminator->insertInto(block, block->begin());
+      else
+        potentialTerminator->insertAfter(&block->back());
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kiranchandramohan wrote:

Nit: braces might be useful here.

https://github.com/llvm/llvm-project/pull/96052