[Mlir-commits] [mlir] [mlir][ArmSVE] Add `arm_sve.psel` operation (PR #95764)

[Cullen Rhodes]

================
@@ -442,6 +442,43 @@ def ZipX4Op  : ArmSVE_Op<"zip.x4", [
   }];
 }
 
+def PselOp : ArmSVE_Op<"psel", [
+  Pure,
+  AllTypesMatch<["p1", "result"]>,
+]> {
+  let summary = "Predicate select";
+
+  let description = [{
+    This operation returns the input predicate `p1` or an all-false predicate
+    based on the bit at `p2[index]`. Informally the semantics are:
+    ```
+    if p2[index % num_elements(p2)] == 1:
+      return p1 : type(p1)
+    return all-false : type(p1)
+    ```
+
+    Example:
+    ```mlir
+    // Note: p1 and p2 can have different sizes.
+    %pd = arm_sve.psel %p1, %p2[%index] : vector<[4]xi1>, vector<[8]xi1>
+    ```
+
+    Note: This requires SME or SVE2 (`+sme` or `+sve2` in LLVM target features).
----------------
c-rhodes wrote:

Feature is SVE2.1
https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions/PSEL--Predicate-select-between-predicate-register-or-all-false-

```suggestion
    Note: This requires SME or SVE2.1 (`+sme` or `+sve2p1` in LLVM target features).
```

https://github.com/llvm/llvm-project/pull/95764