[Mlir-commits] [mlir] [mlir][vector] Remove Emulated Sub-directory (PR #94742)

[llvmlistbot at llvm.org]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-mlir-vector

Author: Mubashar Ahmad (mub-at-arm)

<details>
<summary>Changes</summary>

The "Emulated" sub-directory under "ArmSVE" has
been removed. Associated tests have been up a
directory and now include the "REQUIRES"
constraint for the arm-emulator.

---
Full diff: https://github.com/llvm/llvm-project/pull/94742.diff


5 Files Affected:

- (removed) mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/lit.local.cfg (-5) 
- (removed) mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-scalable-deinterleave.mlir (-30) 
- (removed) mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-setArmVLBits.mlir (-46) 
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/lit.local.cfg (+5) 
- (modified) mlir/test/lit.cfg.py (+3) 


``````````diff
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/lit.local.cfg b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/lit.local.cfg
deleted file mode 100644
index 0d8ad605f598f..0000000000000
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/lit.local.cfg
+++ /dev/null
@@ -1,5 +0,0 @@
-# The tests in this folder assume full control of the hardware features, such as
-# the vector length, so must be run under an emulator.
-
-if not config.arm_emulator_executable:
-    config.unsupported = True
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-scalable-deinterleave.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-scalable-deinterleave.mlir
deleted file mode 100644
index e6c561437132f..0000000000000
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-scalable-deinterleave.mlir
+++ /dev/null
@@ -1,30 +0,0 @@
-// DEFINE: %{entry_point} = entry
-// DEFINE: %{compile} = mlir-opt %s -test-lower-to-llvm
-// DEFINE: %{run} = %mcr_aarch64_cmd -march=aarch64 -mattr=+sve \
-// DEFINE:  -e %{entry_point} -entry-point-result=void \
-// DEFINE:  -shared-libs=%mlir_c_runner_utils,%mlir_arm_runner_utils
-
-// RUN: %{compile} | %{run} | FileCheck %s
-
-func.func @entry() {
-  // Set the vector length to 256-bit (equivalent to vscale=2).
-  // This allows the checks (below) to look at an entire vector.
-  %c256 = arith.constant 256 : i32
-  func.call @setArmVLBits(%c256) : (i32) -> ()
-  func.call @test_deinterleave() : () -> ()
-  return
-}
-
-func.func @test_deinterleave() {
-  %step_vector = llvm.intr.experimental.stepvector : vector<[4]xi8>
-  vector.print %step_vector : vector<[4]xi8>
-  // CHECK: ( 0, 1, 2, 3, 4, 5, 6, 7 )
-  %v1, %v2 = vector.deinterleave %step_vector : vector<[4]xi8> -> vector<[2]xi8>
-  vector.print %v1 : vector<[2]xi8>
-  vector.print %v2 : vector<[2]xi8>
-  // CHECK: ( 0, 2, 4, 6 )
-  // CHECK: ( 1, 3, 5, 7 )
-  return
-}
-
-func.func private @setArmVLBits(%bits : i32)
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-setArmVLBits.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-setArmVLBits.mlir
deleted file mode 100644
index aa8d0e4d5104a..0000000000000
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-setArmVLBits.mlir
+++ /dev/null
@@ -1,46 +0,0 @@
-// DEFINE: %{entry_point} = main
-// DEFINE: %{compile} = mlir-opt %s -test-lower-to-llvm
-// DEFINE: %{run} = %mcr_aarch64_cmd -march=aarch64 -mattr=+sve \
-// DEFINE:  -e %{entry_point} -entry-point-result=void \
-// DEFINE:  -shared-libs=%mlir_runner_utils,%mlir_c_runner_utils,%mlir_arm_runner_utils
-
-// RUN: %{compile} | %{run} | FileCheck %s
-
-func.func @checkVScale() {
-  %vscale = vector.vscale
-  vector.print str "vscale = "
-  vector.print %vscale : index
-  return
-}
-
-func.func @setAndCheckVL(%bits: i32) {
-  func.call @setArmVLBits(%bits) : (i32) -> ()
-  func.call @checkVScale() : () -> ()
-  return
-}
-
-func.func @main() {
-  //      CHECK: vscale = 1
-  %c128 = arith.constant 128 : i32
-  func.call @setAndCheckVL(%c128) : (i32) -> ()
-
-  //      CHECK: vscale = 2
-  %c256 = arith.constant 256 : i32
-  func.call @setAndCheckVL(%c256) : (i32) -> ()
-
-  //      CHECK: vscale = 4
-  %c512 = arith.constant 512 : i32
-  func.call @setAndCheckVL(%c512) : (i32) -> ()
-
-  //      CHECK: vscale = 8
-  %c1024 = arith.constant 1024 : i32
-  func.call @setAndCheckVL(%c1024) : (i32) -> ()
-
-  //      CHECK: vscale = 16
-  %c2048 = arith.constant 2048 : i32
-  func.call @setAndCheckVL(%c2048) : (i32) -> ()
-
-  return
-}
-
-func.func private @setArmVLBits(%bits : i32)
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/lit.local.cfg b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/lit.local.cfg
index 37d3a74874ce4..ec61ead8838ba 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/lit.local.cfg
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/lit.local.cfg
@@ -7,3 +7,8 @@ if not config.mlir_run_arm_sve_tests:
 # No JIT on win32.
 if sys.platform == "win32":
     config.unsupported = True
+
+# The tests in this folder assume full control of the hardware features, such as
+# the vector length, so must be run under an emulator.
+if not config.arm_emulator_executable:
+    config.unsupported = True
diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py
index 9ed3a2efcb8f7..525feac8f9a14 100644
--- a/mlir/test/lit.cfg.py
+++ b/mlir/test/lit.cfg.py
@@ -250,3 +250,6 @@ def have_host_jit_feature_support(feature_name):
 
 if config.run_rocm_tests:
     config.available_features.add("host-supports-amdgpu")
+
+if config.arm_emulator_executable:
+    config.available_features.add("arm-emulator-executable")

``````````

</details>


https://github.com/llvm/llvm-project/pull/94742