[Mlir-commits] [mlir] [MLIR][AMDGPU] Add amdgpu.sched_barrier (PR #98911)

[Lei Zhang]

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@@ -433,6 +433,46 @@ def AMDGPU_LDSBarrierOp : AMDGPU_Op<"lds_barrier"> {
   let assemblyFormat = "attr-dict";
 }
 
+def AMDGPU_SchedBarrierOpOpt : I32BitEnumAttr<"sched_barrier_opt_enum",
+    "The possible options for scheduling barriers",
+    [
+      I32BitEnumAttrCaseBit<"allow_none", 0>,
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antiagainst wrote:

Note that `0` here means the `0`-th bit is set, not meaning all bits are unset (which is `I32BitEnumAttrCaseNone`. Just wanted to double check--do we actually have the `0`-th bit set to mean allowing nothing?

https://github.com/llvm/llvm-project/pull/98911