[Mlir-commits] [mlir] [mlir][affine] Fix the crash due to the simultaneous replacement store (PR #90829)
Kai Sasaki
llvmlistbot at llvm.org
Sun Jul 7 19:38:11 PDT 2024
https://github.com/Lewuathe updated https://github.com/llvm/llvm-project/pull/90829
>From 0e00155d0e6a7a57255438dc98558478f3b58320 Mon Sep 17 00:00:00 2001
From: Kai Sasaki <lewuathe at gmail.com>
Date: Thu, 2 May 2024 16:37:12 +0900
Subject: [PATCH] [mlir][affine] Fix the crash due to the simultaneous
replacement store
---
mlir/lib/Dialect/Affine/Utils/Utils.cpp | 3 +--
mlir/test/Dialect/Affine/scalrep.mlir | 21 +++++++++++++++++++++
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/mlir/lib/Dialect/Affine/Utils/Utils.cpp b/mlir/lib/Dialect/Affine/Utils/Utils.cpp
index 8b8ed2578ca5cc..eba6446c5f8896 100644
--- a/mlir/lib/Dialect/Affine/Utils/Utils.cpp
+++ b/mlir/lib/Dialect/Affine/Utils/Utils.cpp
@@ -866,8 +866,7 @@ static void forwardStoreToLoad(AffineReadOpInterface loadOp,
// 3. The store must reach the load. Access function equivalence only
// guarantees this for accesses in the same block. The load could be in a
// nested block that is unreachable.
- if (storeOp->getBlock() != loadOp->getBlock() &&
- !mustReachAtInnermost(srcAccess, destAccess))
+ if (!mustReachAtInnermost(srcAccess, destAccess))
continue;
// 4. Ensure there is no intermediate operation which could replace the
diff --git a/mlir/test/Dialect/Affine/scalrep.mlir b/mlir/test/Dialect/Affine/scalrep.mlir
index 22d394bfcf0979..6432efb6a435bb 100644
--- a/mlir/test/Dialect/Affine/scalrep.mlir
+++ b/mlir/test/Dialect/Affine/scalrep.mlir
@@ -5,6 +5,7 @@
// CHECK-DAG: [[$MAP2:#map[0-9]*]] = affine_map<(d0, d1) -> (d1)>
// CHECK-DAG: [[$MAP3:#map[0-9]*]] = affine_map<(d0, d1) -> (d0 - 1)>
// CHECK-DAG: [[$MAP4:#map[0-9]*]] = affine_map<(d0) -> (d0 + 1)>
+// CHECK-DAG: [[$IDENT:#map[0-9]*]] = affine_map<(d0) -> (d0)>
// CHECK-LABEL: func @simple_store_load() {
func.func @simple_store_load() {
@@ -913,3 +914,23 @@ func.func @cross_block() {
%69 = affine.load %alloc_99[%c10] : memref<13xi1>
return
}
+
+#map1 = affine_map<(d0) -> (d0)>
+
+// CHECK-LABEL: func @consecutive_store
+func.func @consecutive_store() {
+ // CHECK: %[[CST:.*]] = arith.constant
+ %tmp = arith.constant 1.1 : f16
+ // CHECK: %[[ALLOC:.*]] = memref.alloc
+ %alloc_66 = memref.alloc() : memref<f16, 1>
+ affine.for %arg2 = 4 to 6 {
+ affine.for %arg3 = #map1(%arg2) to #map1(%arg2) step 4 {
+ // CHECK: affine.store %[[CST]], %[[ALLOC]][]
+ affine.store %tmp, %alloc_66[] : memref<f16, 1>
+ // CHECK-NOT: affine.store %[[CST]], %[[ALLOC]][]
+ affine.store %tmp, %alloc_66[] : memref<f16, 1>
+ %270 = affine.load %alloc_66[] : memref<f16, 1>
+ }
+ }
+ return
+}
More information about the Mlir-commits
mailing list