[Mlir-commits] [libcxx] [flang] [clang-tools-extra] [compiler-rt] [mlir] [llvm] [lldb] [libc] [clang] [AArch64] add intrinsic to generate a bfi instruction (PR #79672)

[Dawei Pan]

dwpan wrote:

> Hello. Can you explain why this is needed, as opposed to using the equivalent shift/and/ors?

In Verilog/SystemVerilog language, the basic type is bit or bit vector, and length is arbitrary, insert/extract bits are common features in language. Introducing corresponding intrinsics could help gradually lower it and bring more optimization opportunities in llc.   Otherwise, many shift/and/or are needed to be translated and then depends on code pattern matching to recognize and optimize them.     

https://github.com/llvm/llvm-project/pull/79672