[Mlir-commits] [mlir] [mlir][ArmSME] Add initial SME vector legalization pass (PR #79152)

[Benjamin Maxwell]

MacDue wrote:

I've made added some more context to the header of the pass, that within this context `tile` always means SME tile (and renamed most things to say `smeTile`).  

> Another option that could help disambiguate:
> 
> * `ZATile` to represent e.g. `vector<[8]x[8]xi32>`, and
> * `ZASubTile` for things like `vector<[4]x[4]xi32>`.
> 
> These would be different for different element types.

This pass is not considering ZA, the input `vectorType` does not have map to the size of ZA, it can be bigger, smaller, or the same size, but that's not the concern of this pass. This pass just wants to convert operations on `vectorTypes` that are some multiple of SME tiles, into multiple SME-sized operations. 


https://github.com/llvm/llvm-project/pull/79152