[Mlir-commits] [mlir] [mlir][Vector] Add patterns for efficient i4 -> i8 conversion emulation (PR #79494)

[Diego Caballero]

dcaballe wrote:

> Out of curiosity, how hard would it be to have foldings from the existing in MLIR to get to a similar form like you have now?

It seems complicated as the approach seems slightly different. We would have to look at multiple ops to realize that the first shuffle is redundant for cases that are multiple of the 8 bits ("aligned"). Then realize that some of the shifts are actually implementing the interleave of two register... I don't see a clear path...

> Any thoughts/plans for extending this to scalable vectors? Related discussion here: https://github.com/llvm/llvm-project/pull/79270

This is mostly a workaround to keep things moving but ultimately we may want these simpler cases to be implemented in the backend (there were already a few comments about that in this file). It gets difficult to get this working for scalable at this level as we would have to introduce SVE or LLVM intrinsics to model the interleave in an scalable way. The current implementation is also not working for multi-dim vectors (multi-dim not supported by shuffle), which is another limitation that we are hitting at this level with this PR.

https://github.com/llvm/llvm-project/pull/79494