[Mlir-commits] [libcxxabi] [flang] [mlir] [clang-tools-extra] [clang] [libcxx] [compiler-rt] [llvm] [openmp] [libc] [AArch64] Combine store (trunc X to <3 x i8>) to sequence of ST1.b. (PR #78637)

[Eli Friedman]

================
@@ -281,23 +279,19 @@ entry:
 define void @store_trunc_add_from_64bits(ptr %src, ptr %dst) {
 ; CHECK-LABEL: store_trunc_add_from_64bits:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub sp, sp, #16
-; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    ldr s0, [x0]
 ; CHECK-NEXT:    add x9, x0, #4
 ; CHECK-NEXT:  Lloh0:
 ; CHECK-NEXT:    adrp x8, lCPI7_0 at PAGE
 ; CHECK-NEXT:  Lloh1:
 ; CHECK-NEXT:    ldr d1, [x8, lCPI7_0 at PAGEOFF]
+; CHECK-NEXT:    add x8, x1, #1
 ; CHECK-NEXT:    ld1.h { v0 }[2], [x9]
+; CHECK-NEXT:    add x9, x1, #2
 ; CHECK-NEXT:    add.4h v0, v0, v1
-; CHECK-NEXT:    xtn.8b v1, v0
-; CHECK-NEXT:    umov.h w8, v0[2]
-; CHECK-NEXT:    str s1, [sp, #12]
-; CHECK-NEXT:    ldrh w9, [sp, #12]
----------------
efriedma-quic wrote:

v4i8 and v2i16 aren't legal types.  And the legalization rule we use for them is "promote", so the bitcast isn't a no-op. There's padding between the elements.  So we need to do a shuffle... but neither AArch64TargetLowering::ReplaceBITCASTResults nor DAGTypeLegalizer::PromoteIntRes_BITCAST has code to do that, so we end up using CreateStackStoreLoad.

The legalization rule for vector types is under the control of the target; see AArch64TargetLowering::getPreferredVectorAction.  You can use that to force v4i8->v8i8.  But changing that impacts a lot of code.

https://github.com/llvm/llvm-project/pull/78637