[Mlir-commits] [mlir] [mlir][ArmSME] Support widening outer products (PR #78975)

[Andrzej Warzyński]

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@@ -410,4 +410,8 @@ def ConvertToSvboolIntrOp :
     /*overloadedResults=*/[]>,
     Arguments<(ins SVEPredicate:$mask)>;
 
+def Zip1IntrOp :
+  ArmSVE_IntrBinaryOverloadedOp<"zip1">,
+  Arguments<(ins AnyScalableVector, AnyScalableVector)>;
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banach-space wrote:

> I know the other intrinsics don't bother, but this can't take AnyScalableVector, it can only take vectors that exactly match the size of a hardware SVE vector.

Why? As in, what's the difference between this and other intrinsics? Is it something from the ISA that I am missing?

Also, @c-rhodes , thinking how to split this massive patch - would you mind moving `zip1` to a dedicated PR?

https://github.com/llvm/llvm-project/pull/78975