[Mlir-commits] [mlir] [mlir][vector] Extend vector.{insert|extract}_strided_slice (PR #79052)

Cullen Rhodes llvmlistbot at llvm.org
Tue Jan 23 05:55:25 PST 2024


================
@@ -3265,6 +3288,20 @@ LogicalResult ExtractStridedSliceOp::verify() {
   if (getResult().getType() != resultType)
     return emitOpError("expected result type to be ") << resultType;
 
+  unsigned idx = 0;
+  for (unsigned ub = sizes.size(); idx < ub; ++idx) {
----------------
c-rhodes wrote:

nit: the ind/ub var initialization is a bit unusual, why not?
```suggestion
  for (unsigned idx = 0; idx < sizes.size(); ++idx) {
```

(same applies to insert equivalent)

https://github.com/llvm/llvm-project/pull/79052


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