[Mlir-commits] [mlir] [mlir] Add `mlir_arm_runner_utils` library for use in integration tests (PR #78583)
Benjamin Maxwell
llvmlistbot at llvm.org
Thu Jan 18 07:20:31 PST 2024
https://github.com/MacDue updated https://github.com/llvm/llvm-project/pull/78583
>From 34126e3fcd66e49ceaeaceb34f5bd55fd9af808c Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: Thu, 18 Jan 2024 12:24:31 +0000
Subject: [PATCH 1/2] [mlir] Add `mlir_arm_runner_utils` library for use in
integration tests
This adds a new `mlir_arm_runner_utils` library that contains utils
specific to Arm/AArch64. This is for use in MLIR integration tests.
This initial patch adds `setArmVLBits()` and `setArmSVLBits()`. This
allows changing vector length or streaming vector length at runtime (or
setting it to a known minimum, i.e. 128-bits).
---
mlir/lib/ExecutionEngine/ArmRunnerUtils.cpp | 60 +++++++++++++++
mlir/lib/ExecutionEngine/CMakeLists.txt | 5 ++
mlir/test/CMakeLists.txt | 4 +
.../Vector/CPU/ArmSME/test-setArmSVLBits.mlir | 76 +++++++++++++++++++
.../Vector/CPU/ArmSME/test-setArmVLBits.mlir | 38 ++++++++++
mlir/test/lit.cfg.py | 3 +
6 files changed, 186 insertions(+)
create mode 100644 mlir/lib/ExecutionEngine/ArmRunnerUtils.cpp
create mode 100644 mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmSVLBits.mlir
create mode 100644 mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmVLBits.mlir
diff --git a/mlir/lib/ExecutionEngine/ArmRunnerUtils.cpp b/mlir/lib/ExecutionEngine/ArmRunnerUtils.cpp
new file mode 100644
index 000000000000000..e619c923453cf3b
--- /dev/null
+++ b/mlir/lib/ExecutionEngine/ArmRunnerUtils.cpp
@@ -0,0 +1,60 @@
+//===- ArmRunnerUtils.cpp - Utilities for configuring architecture properties //
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include <iostream>
+#include <stdint.h>
+#include <string_view>
+
+#if (defined(_WIN32) || defined(__CYGWIN__))
+#define MLIR_ARMRUNNERUTILS_EXPORTED __declspec(dllexport)
+#else
+#define MLIR_ARMRUNNERUTILS_EXPORTED __attribute__((visibility("default")))
+#endif
+
+#ifdef __linux__
+#include <sys/prctl.h>
+#endif
+
+extern "C" {
+
+#define PR_VL_LEN_MASK 0xffff
+
+#ifndef PR_SVE_SET_VL
+#define PR_SVE_SET_VL 50
+#endif
+
+#ifndef PR_SME_SET_VL
+#define PR_SME_SET_VL 63
+#endif
+
+static void setArmVectorLength(std::string_view helper_name, int option,
+ int bits) {
+#if defined(__linux__) && defined(__aarch64__)
+ if (bits < 128 || bits % 128 != 0 || bits > 2048) {
+ std::cerr << "[error] Invalid aarch64 vector length!" << std::endl;
+ abort();
+ }
+ uint32_t vl = bits / 8;
+ if (prctl(option, vl & PR_VL_LEN_MASK) == -1) {
+ std::cerr << "[error] prctl failed!" << std::endl;
+ abort();
+ }
+#else
+ std::cerr << "[error] " << helper_name << " is unsupported!" << std::endl;
+ abort();
+#endif
+}
+
+void MLIR_ARMRUNNERUTILS_EXPORTED setArmVLBits(uint32_t bits) {
+ setArmVectorLength(__func__, PR_SVE_SET_VL, bits);
+}
+
+void MLIR_ARMRUNNERUTILS_EXPORTED setArmSVLBits(uint32_t bits) {
+ setArmVectorLength(__func__, PR_SME_SET_VL, bits);
+}
+}
diff --git a/mlir/lib/ExecutionEngine/CMakeLists.txt b/mlir/lib/ExecutionEngine/CMakeLists.txt
index 2f391b7698cbb02..b7e448d5417ea91 100644
--- a/mlir/lib/ExecutionEngine/CMakeLists.txt
+++ b/mlir/lib/ExecutionEngine/CMakeLists.txt
@@ -2,6 +2,7 @@
# is a big dependency which most don't need.
set(LLVM_OPTIONAL_SOURCES
+ ArmRunnerUtils.cpp
ArmSMEStubs.cpp
AsyncRuntime.cpp
CRunnerUtils.cpp
@@ -186,6 +187,10 @@ if(LLVM_ENABLE_PIC)
ArmSMEStubs.cpp)
target_compile_definitions(mlir_arm_sme_abi_stubs PRIVATE mlir_arm_sme_abi_stubs_EXPORTS)
+ add_mlir_library(mlir_arm_runner_utils
+ SHARED
+ ArmRunnerUtils.cpp)
+
if(MLIR_ENABLE_CUDA_RUNNER)
# Configure CUDA support. Using check_language first allows us to give a
# custom error message.
diff --git a/mlir/test/CMakeLists.txt b/mlir/test/CMakeLists.txt
index 8ce030feeded92a..6724dd4bdd1bcd4 100644
--- a/mlir/test/CMakeLists.txt
+++ b/mlir/test/CMakeLists.txt
@@ -153,6 +153,10 @@ if (MLIR_RUN_ARM_SME_TESTS AND NOT ARM_SME_ABI_ROUTINES_SHLIB)
list(APPEND MLIR_TEST_DEPENDS mlir_arm_sme_abi_stubs)
endif()
+if (MLIR_RUN_ARM_SVE_TESTS OR MLIR_RUN_ARM_SME_TESTS)
+ list(APPEND MLIR_TEST_DEPENDS mlir_arm_runner_utils)
+endif()
+
list(APPEND MLIR_TEST_DEPENDS MLIRUnitTests)
if(LLVM_BUILD_EXAMPLES)
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmSVLBits.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmSVLBits.mlir
new file mode 100644
index 000000000000000..3e7e72df665c3ff
--- /dev/null
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmSVLBits.mlir
@@ -0,0 +1,76 @@
+// DEFINE: %{entry_point} = main
+// DEFINE: %{compile} = mlir-opt %s -convert-arm-sme-to-llvm \
+// DEFINE: -cse -canonicalize -test-lower-to-llvm
+// DEFINE: %{run} = %mcr_aarch64_cmd \
+// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -e %{entry_point} -entry-point-result=void \
+// DEFINE: -shared-libs=%mlir_runner_utils,%mlir_c_runner_utils,%mlir_arm_runner_utils
+
+// RUN: %{compile} | %{run} | FileCheck %s
+
+func.func @checkSVL() {
+ %svl_b = arm_sme.streaming_vl <byte>
+ %svl_h = arm_sme.streaming_vl <half>
+ %svl_w = arm_sme.streaming_vl <word>
+ %svl_d = arm_sme.streaming_vl <double>
+ vector.print str "SVL.b"
+ vector.print %svl_b : index
+ vector.print str "SVL.h"
+ vector.print %svl_h : index
+ vector.print str "SVL.w"
+ vector.print %svl_w : index
+ vector.print str "SVL.d"
+ vector.print %svl_d : index
+ return
+}
+
+func.func @main() {
+ // CHECK: SVL.b
+ // CHECK-NEXT: 16
+ //
+ // CHECK-NEXT: SVL.h
+ // CHECK-NEXT: 8
+ //
+ // CHECK-NEXT: SVL.w
+ // CHECK-NEXT: 4
+ //
+ // CHECK-NEXT: SVL.d
+ // CHECK-NEXT: 2
+ %c128 = arith.constant 128 : i32
+ func.call @setArmSVLBits(%c128) : (i32) -> ()
+ func.call @checkSVL() : () -> ()
+
+ // CHECK: SVL.b
+ // CHECK-NEXT: 32
+ //
+ // CHECK-NEXT: SVL.h
+ // CHECK-NEXT: 16
+ //
+ // CHECK-NEXT: SVL.w
+ // CHECK-NEXT: 8
+ //
+ // CHECK-NEXT: SVL.d
+ // CHECK-NEXT: 4
+ %c256 = arith.constant 256 : i32
+ func.call @setArmSVLBits(%c256) : (i32) -> ()
+ func.call @checkSVL() : () -> ()
+
+ // CHECK: SVL.b
+ // CHECK-NEXT: 64
+ //
+ // CHECK-NEXT: SVL.h
+ // CHECK-NEXT: 32
+ //
+ // CHECK-NEXT: SVL.w
+ // CHECK-NEXT: 16
+ //
+ // CHECK-NEXT: SVL.d
+ // CHECK-NEXT: 8
+ %c512 = arith.constant 512 : i32
+ func.call @setArmSVLBits(%c512) : (i32) -> ()
+ func.call @checkSVL() : () -> ()
+
+ return
+}
+
+func.func private @setArmSVLBits(%bits : i32)
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmVLBits.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmVLBits.mlir
new file mode 100644
index 000000000000000..ad7a29d47d068ed
--- /dev/null
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmVLBits.mlir
@@ -0,0 +1,38 @@
+// DEFINE: %{entry_point} = main
+// DEFINE: %{compile} = mlir-opt %s -convert-arm-sme-to-llvm \
+// DEFINE: -cse -canonicalize -test-lower-to-llvm
+// DEFINE: %{run} = %mcr_aarch64_cmd \
+// DEFINE: -march=aarch64 -mattr=+sve,+sme \
+// DEFINE: -e %{entry_point} -entry-point-result=void \
+// DEFINE: -shared-libs=%mlir_runner_utils,%mlir_c_runner_utils,%mlir_arm_runner_utils
+
+// RUN: %{compile} | %{run} | FileCheck %s
+
+/// Note: This is included in the SME tests rather than the SVE tests as it is
+/// safe to assume the SME tests will be ran on an emulator, so will be able to
+/// change the vector length.
+
+func.func @checkVScale() {
+ %vscale = vector.vscale
+ vector.print str "vscale"
+ vector.print %vscale : index
+ return
+}
+
+func.func @main() {
+ // CHECK: vscale
+ // CHECK-NEXT: 1
+ %c128 = arith.constant 128 : i32
+ func.call @setArmVLBits(%c128) : (i32) -> ()
+ func.call @checkVScale() : () -> ()
+
+ // CHECK: vscale
+ // CHECK-NEXT: 2
+ %c256 = arith.constant 256 : i32
+ func.call @setArmVLBits(%c256) : (i32) -> ()
+ func.call @checkVScale() : () -> ()
+
+ return
+}
+
+func.func private @setArmVLBits(%bits : i32)
diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py
index 0a1ea1d16da4523..38e65e4549c5595 100644
--- a/mlir/test/lit.cfg.py
+++ b/mlir/test/lit.cfg.py
@@ -135,6 +135,9 @@ def add_runtime(name):
if config.enable_sycl_runner:
tools.extend([add_runtime("mlir_sycl_runtime")])
+if config.mlir_run_arm_sve_tests or config.mlir_run_arm_sme_tests:
+ tools.extend([add_runtime("mlir_arm_runner_utils")])
+
if config.mlir_run_arm_sme_tests:
config.substitutions.append(
(
>From 82381e1256972a5ff2934d59d8fe559bdecd0e64 Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: Thu, 18 Jan 2024 15:13:40 +0000
Subject: [PATCH 2/2] Move setArmSVLBits()/setArmVLBits() tests into "Emulated"
subdir
These tests assume the hardware's vector length is >= the max VL they
set. This cannot be guaranteed for all hardware configurations unless
these tests are emulated.
---
.../Dialect/Vector/CPU/ArmSME/Emulated/lit.local.cfg | 5 +++++
.../Vector/CPU/ArmSME/{ => Emulated}/test-setArmSVLBits.mlir | 0
.../Dialect/Vector/CPU/ArmSVE/Emulated/lit.local.cfg | 5 +++++
.../CPU/{ArmSME => ArmSVE/Emulated}/test-setArmVLBits.mlir | 4 ----
4 files changed, 10 insertions(+), 4 deletions(-)
create mode 100644 mlir/test/Integration/Dialect/Vector/CPU/ArmSME/Emulated/lit.local.cfg
rename mlir/test/Integration/Dialect/Vector/CPU/ArmSME/{ => Emulated}/test-setArmSVLBits.mlir (100%)
create mode 100644 mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/lit.local.cfg
rename mlir/test/Integration/Dialect/Vector/CPU/{ArmSME => ArmSVE/Emulated}/test-setArmVLBits.mlir (83%)
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/Emulated/lit.local.cfg b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/Emulated/lit.local.cfg
new file mode 100644
index 000000000000000..0d8ad605f598fb0
--- /dev/null
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/Emulated/lit.local.cfg
@@ -0,0 +1,5 @@
+# The tests in this folder assume full control of the hardware features, such as
+# the vector length, so must be run under an emulator.
+
+if not config.arm_emulator_executable:
+ config.unsupported = True
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmSVLBits.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/Emulated/test-setArmSVLBits.mlir
similarity index 100%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmSVLBits.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSME/Emulated/test-setArmSVLBits.mlir
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/lit.local.cfg b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/lit.local.cfg
new file mode 100644
index 000000000000000..0d8ad605f598fb0
--- /dev/null
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/lit.local.cfg
@@ -0,0 +1,5 @@
+# The tests in this folder assume full control of the hardware features, such as
+# the vector length, so must be run under an emulator.
+
+if not config.arm_emulator_executable:
+ config.unsupported = True
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmVLBits.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-setArmVLBits.mlir
similarity index 83%
rename from mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmVLBits.mlir
rename to mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-setArmVLBits.mlir
index ad7a29d47d068ed..a77d5d96138a80b 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmVLBits.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-setArmVLBits.mlir
@@ -8,10 +8,6 @@
// RUN: %{compile} | %{run} | FileCheck %s
-/// Note: This is included in the SME tests rather than the SVE tests as it is
-/// safe to assume the SME tests will be ran on an emulator, so will be able to
-/// change the vector length.
-
func.func @checkVScale() {
%vscale = vector.vscale
vector.print str "vscale"
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